17 lines
270 B
Verilog
17 lines
270 B
Verilog
`ifndef _or_v
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`define _or_v
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`include "nand.v"
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`include "not.v"
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module Or (input a, input b, output out);
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wire a_bar;
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wire b_bar;
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Not u1(.in(a), .out(a_bar));
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Not u2(.in(b), .out(b_bar));
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Nand u3(.a(a_bar), .b(b_bar), .out(out));
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endmodule
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`endif
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