sci-electronics/yosys: version bump
dev-embedded/rpi-imager: fixes
This commit is contained in:
@@ -11,8 +11,8 @@ KEYWORDS="amd64 aarch64"
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S=$WORKDIR/$P/src
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DEPEND="
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dev-qt/qtbase:5
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dev-qt/qtdbus:5
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dev-qt/qtbase
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dev-qt/qtdbus
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sys-libs/zlib
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app-arch/lzma
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|| ( net-libs/gnutls dev-libs/openssl )
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@@ -1,6 +1,6 @@
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BDEPEND=app-alternatives/ninja >=dev-build/cmake-3.20.5
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DEFINED_PHASES=compile configure install prepare test
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DEPEND=dev-qt/qtbase:5 dev-qt/qtdbus:5 sys-libs/zlib app-arch/lzma || ( net-libs/gnutls dev-libs/openssl )
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DEPEND=dev-qt/qtbase dev-qt/qtdbus sys-libs/zlib app-arch/lzma || ( net-libs/gnutls dev-libs/openssl )
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DESCRIPTION=Raspberry Pi Imaging Utility
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EAPI=8
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HOMEPAGE=https://www.raspberrypi.com/software/
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@@ -10,4 +10,4 @@ LICENSE=Apache-2.0
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SLOT=0
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SRC_URI=https://github.com/raspberrypi/rpi-imager/archive/refs/tags/v1.8.5.tar.gz -> rpi-imager-1.8.5.tar.gz
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_eclasses_=cmake c7c9a62d6232cac66d4ea32d575c3e7c flag-o-matic d309b9713dfc18e754cba88d3ba69653 multilib c19072c3cd7ac5cb21de013f7e9832e0 multiprocessing 30ead54fa2e2b5f9cd4e612ffc34d0fe ninja-utils 2df4e452cea39a9ec8fb543ce059f8d6 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 xdg-utils baea6080dd821f5562d715887954c9d3
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_md5_=d70121da4c3f61111c218d340d58d2fd
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_md5_=a616937e6543c0e5a9b45f3f6034b772
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@@ -1,10 +0,0 @@
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DEFINED_PHASES=compile install unpack
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DEPEND=dev-vcs/git media-gfx/xdot dev-libs/boost sys-devel/clang
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DESCRIPTION=framework for Verilog RTL synthesis
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EAPI=8
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HOMEPAGE=http://www.clifford.at/yosys/
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KEYWORDS=amd64
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LICENSE=ISC
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SLOT=0
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SRC_URI=https://github.com/YosysHQ/yosys/archive/yosys-0.41.tar.gz https://github.com/YosysHQ/abc/archive/237d81397fcc85dd3894bf1a449d2955cd3df02d.tar.gz -> abc-237d81397fcc85dd3894bf1a449d2955cd3df02d.tar.gz
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_md5_=21e950debb2ebffee114669546da1711
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13
metadata/md5-cache/sci-electronics/yosys-0.42
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13
metadata/md5-cache/sci-electronics/yosys-0.42
Normal file
@@ -0,0 +1,13 @@
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BDEPEND=>=dev-vcs/git-1.8.2.1[curl]
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DEFINED_PHASES=compile install unpack
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DEPEND=dev-vcs/git media-gfx/xdot dev-libs/boost sys-devel/clang
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DESCRIPTION=framework for Verilog RTL synthesis
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EAPI=8
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HOMEPAGE=http://www.clifford.at/yosys/
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INHERIT=git-r3
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KEYWORDS=amd64
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LICENSE=ISC
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PROPERTIES=live
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SLOT=0
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_eclasses_=git-r3 fbb2889c81f3a05910c1524db69425c1
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_md5_=818fce1ba7932700279869c3a92bac2c
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@@ -1,5 +1,5 @@
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BDEPEND=>=dev-vcs/git-1.8.2.1[curl]
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DEFINED_PHASES=compile configure install prepare unpack
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DEFINED_PHASES=compile install unpack
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DEPEND=dev-vcs/git media-gfx/xdot dev-libs/boost sys-devel/clang
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DESCRIPTION=framework for Verilog RTL synthesis
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EAPI=8
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@@ -8,6 +8,5 @@ INHERIT=git-r3
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LICENSE=ISC
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PROPERTIES=live
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SLOT=0
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SRC_URI=https://github.com/YosysHQ/abc/archive/bb64142b07794ee685494564471e67365a093710.tar.gz -> abc-bb64142b07794ee685494564471e67365a093710.tar.gz
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_eclasses_=git-r3 fbb2889c81f3a05910c1524db69425c1
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_md5_=158bb2afa140131adcfe2c0cb05589eb
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_md5_=0a311225681b9e5ae66e82936d318716
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@@ -1,3 +0,0 @@
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DIST abc-237d81397fcc85dd3894bf1a449d2955cd3df02d.tar.gz 6213042 BLAKE2B 490ce60da678f679db2339ff46d17c50257ac077c63de6881104e5e25e29bf82c7488b2620335803024cbbd2a04bc35e90dfa14e521f5708cc9a1617237c7d70 SHA512 f9585094d657495241bb8625f1e907c9abda3bfd691937c49062a344a69a5b96693865bf20f1448f6e66cadceeb7602cb747ca2be0c60fdbd4093d1bfa95f6b0
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DIST abc-bb64142b07794ee685494564471e67365a093710.tar.gz 6119314 BLAKE2B b467a1d58abced487b239fd83209eb9a2676f65f94caa7dec1dbcb8a1076169e03ef0a9ac6526ff6b5381561bb3d4b879c892e66705a319567b39d9c003d0061 SHA512 3953b66b7eb68c908c03f6179884c45ecdf0769eb4166e12b137e7f5421c1ab51c556d70f275a86d857b35968d5255a528ade86fd59790fd80449302140490d2
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DIST yosys-0.41.tar.gz 2808657 BLAKE2B ae8f78b1dc0e83c6bd9d9504334f36ae7114ebb25792de8166b5f8d1f00368aa3f8c3c045ee43bc22e63468e2c5a9d4a89b4fdf4c24a5f224e293bf70a236fe2 SHA512 e662f7a8c2c9296f6fce295651f1ef5b815710015533271531c82b19711b969b29165f028f878e02af831b7578a433d02823e515b2ab2415834b6222cd220371
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31
sci-electronics/yosys/files/yosys-makefile.patch
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31
sci-electronics/yosys/files/yosys-makefile.patch
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@@ -0,0 +1,31 @@
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--- a/Makefile 2024-06-07 18:34:14.000000000 -0700
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+++ a/Makefile 2024-06-07 18:34:51.863171714 -0700
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@@ -745,27 +745,7 @@
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.PHONY: check-git-abc
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check-git-abc:
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- @if [ ! -d "$(YOSYS_SRC)/abc" ]; then \
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- echo "Error: The 'abc' directory does not exist."; \
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- echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
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- exit 1; \
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- elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
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- exit 0; \
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- elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
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- echo "'abc' comes from a tarball. Continuing."; \
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- exit 0; \
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- elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
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- echo "Error: 'abc' is not configured as a git submodule."; \
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- echo "To resolve this:"; \
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- echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \
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- echo "2. Remove the existing 'abc' directory: Delete the 'abc' directory and all its contents."; \
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- echo "3. Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
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- echo "4. Reapply your changes: Move your saved changes back to the 'abc' directory, if necessary."; \
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- exit 1; \
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- else \
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- echo "Initialize the submodule: Run 'git submodule update --init' to set up 'abc' as a submodule."; \
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- exit 1; \
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- fi
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+ exit 0;
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abc/abc$(EXE) abc/libabc.a: check-git-abc
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$(P)
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@@ -1,33 +0,0 @@
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EAPI=8
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S=$WORKDIR/$PN-$PN-$PV
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# get the current value from the yosys makefile...look for ABCREV
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ABC_GIT_COMMIT=237d81397fcc85dd3894bf1a449d2955cd3df02d
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DESCRIPTION="framework for Verilog RTL synthesis"
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HOMEPAGE="http://www.clifford.at/yosys/"
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SRC_URI="https://github.com/YosysHQ/$PN/archive/$P.tar.gz
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https://github.com/YosysHQ/abc/archive/$ABC_GIT_COMMIT.tar.gz -> abc-$ABC_GIT_COMMIT.tar.gz"
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LICENSE=ISC
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SLOT=0
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KEYWORDS=amd64
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DEPEND="dev-vcs/git
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media-gfx/xdot
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dev-libs/boost
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sys-devel/clang"
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src_unpack() {
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unpack $P.tar.gz
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unpack abc-$ABC_GIT_COMMIT.tar.gz
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mv $WORKDIR/abc-$ABC_GIT_COMMIT $S/abc
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}
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src_compile() {
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emake DESTDIR="$D" PREFIX=/usr
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}
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src_install() {
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emake DESTDIR="$D" PREFIX=/usr install
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}
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27
sci-electronics/yosys/yosys-0.42.ebuild
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27
sci-electronics/yosys/yosys-0.42.ebuild
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@@ -0,0 +1,27 @@
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EAPI=8
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inherit git-r3
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DESCRIPTION="framework for Verilog RTL synthesis"
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HOMEPAGE="http://www.clifford.at/yosys/"
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EGIT_REPO_URI=https://github.com/YosysHQ/yosys
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EGIT_COMMIT=yosys-0.42
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LICENSE=ISC
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SLOT=0
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KEYWORDS=amd64
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PATCHES=( $FILESDIR/$PN-makefile.patch )
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DEPEND="dev-vcs/git
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media-gfx/xdot
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dev-libs/boost
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sys-devel/clang"
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src_compile()
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{
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emake DESTDIR="$D" PREFIX=/usr
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}
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src_install()
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{
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emake DESTDIR="$D" PREFIX=/usr install
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}
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@@ -2,43 +2,25 @@ EAPI=8
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inherit git-r3
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# get the current value from the yosys makefile...look for ABCREV
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ABC_GIT_COMMIT=bb64142b07794ee685494564471e67365a093710
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DESCRIPTION="framework for Verilog RTL synthesis"
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HOMEPAGE="http://www.clifford.at/yosys/"
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#SRC_URI="https://github.com/YosysHQ/$PN/archive/$GIT_COMMIT.tar.gz -> $P.tar.gz
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SRC_URI="https://github.com/YosysHQ/abc/archive/$ABC_GIT_COMMIT.tar.gz -> abc-$ABC_GIT_COMMIT.tar.gz"
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EGIT_REPO_URI="https://github.com/YosysHQ/yosys"
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EGIT_SUBMODULES=( abc )
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EGIT_REPO_URI=https://github.com/YosysHQ/yosys
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LICENSE=ISC
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SLOT=0
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KEYWORDS=
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PATCHES=( $FILESDIR/$PN-makefile.patch )
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DEPEND="dev-vcs/git
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media-gfx/xdot
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dev-libs/boost
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sys-devel/clang"
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src_unpack() {
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git-r3_fetch $EGIT_REPO_URI
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git-r3_checkout $EGIT_REPO_URI
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unpack abc-$ABC_GIT_COMMIT.tar.gz
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src_compile()
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{
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emake DESTDIR="$D" PREFIX=/usr
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}
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src_prepare() {
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default_src_prepare
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mv $WORKDIR/abc-$ABC_GIT_COMMIT $S/abc
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}
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src_configure() {
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make config-clang
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}
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src_compile() {
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make DESTDIR="$D" ABCREV=default ABCPULL=0 PREFIX=/usr
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}
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src_install() {
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make DESTDIR="$D" ABCREV=default ABCPULL=0 PREFIX=/usr install
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src_install()
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{
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emake DESTDIR="$D" PREFIX=/usr install
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}
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