sci-electronics/yosys: version bump

sci-electronics/yosys/Manifest

@@ -1,3 +1,2 @@
 DIST abc-2c1c83f75b8078ced51f92c697da3e712feb3ac3.tar.gz 6071271 BLAKE2B 46a50ceaec7c98c17440bfadf62a630d15926e3ad34e8addc660b1c50477ed3cd1fe4263e97dd2a31a4f54f076ee84810198d46a5910f9e7d73edcf28cde153a SHA512 b48ac0ee78343f1406c4fc568da769b5d38534a1e7c32bf93acdc25931ed1ee1a7e0e0e55d2099f3a558182a9b58643eefee552eff8c07b0d14a60d96c1ed365
-DIST abc-f6fa2ddcfc89099726d60386befba874c7ac1e0d.tar.gz 5973437 BLAKE2B 889a38df9b123a0a900134c1cddf826741debdc218cd0738b1cb67d6f837a068eb19f76062c407f801837834196a0d61e6957e289d174e34d3666eebff623875 SHA512 708c62384d5c6cc1c603539b30a857b73c9e7b8810718ce6233af732e21aad172e5458f34cefcfdba78b80a33c7a0e9869b8b796ef0bb0bc08e8e7e926e170cc
-DIST yosys-0.28.tar.gz 2520436 BLAKE2B 55f63739b4b1e6fb90d5e0eb4d2b5df05bbc4d8e2f6d61bbbf608f4b2a0ef03a62a0a102f54228f702a110dae78c7b293fb4dc92f5fd61b42540cb59c79d0d57 SHA512 3b7965facdf8c363c6e81f5fd97314e80618f747ea2584af3e5fa010ed45ecae7901ecdb4a9e3525e13d3316959ad0cbc010011ad36669a2467181e4decdf9b1
+DIST yosys-0.29.tar.gz 2524267 BLAKE2B 81a595c6476149f4854ac7ca061483adf023c164bade7b5d37e77a938a45ab754537c00b228a338df8ee1af7dd5fcf4e14b0cbe024ec63ba5dfd8a1f50b90e74 SHA512 f33d78f198576657db9cd558a770e6201a4f9227f01f17c1097b77d50946ec1a001a5ef144cf87958ba6335bb37c2dacde69463d0a98ae1f6754ad0d75def1b9

sci-electronics/yosys/yosys-9999.ebuild

@@ -2,11 +2,8 @@ EAPI=8
 
 inherit git-r3
 
-#GIT_COMMIT=818060880d80b28d483cf5e1c71fcd139d37fe97
-#S=$WORKDIR/$PN-$GIT_COMMIT
-
 # get the current value from the yosys makefile...look for ABCREV
-ABC_GIT_COMMIT=f6fa2ddcfc89099726d60386befba874c7ac1e0d
+ABC_GIT_COMMIT=2c1c83f75b8078ced51f92c697da3e712feb3ac3
 
 DESCRIPTION="framework for Verilog RTL synthesis"
 HOMEPAGE="http://www.clifford.at/yosys/"