Commit Graph

15 Commits

Author SHA1 Message Date
Dominik Sliwa
29fb9d1437 update to the latest symbols and footprints
Update SMTSO2515CTJ standoff and D3 to latest upstream
2022-11-06 17:43:19 +01:00
Stefan Agner
8a27651878 Update silk screen and board version
Adjust silk screen graphics to match current layout. Adjust silk screen
reference designator placements. Bump date and version of schematics and
PCB.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-08-29 18:40:06 +02:00
Dominik Sliwa
e4cf2747aa Yellow 1.3 PCB 2022-08-29 09:09:51 +02:00
Dominik Sliwa
41e283ce0a Add L1/L4 GND pour
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-07-25 10:48:18 +02:00
Dominik Sliwa
f6dc839e95 EMC optimisations
-eth shield is not connected to the GND rather it shields "input" of poe
-used smaller package for bulk PoE capacitor
-Changed common mode filter to Pulse T8113
-Added more inductor filters on the primary side
-replaced secondary side ferrite silter with an inductor
-used distributed "flyback" capacitor (3 instead of 1)
-slightly increased distance between the poe transformer and the
ethernet signal traces
- extended GND1 under the transformer
- primary snubber circuit is now in "hot-loop" area
-repositioned poe enable optocoupler

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-07-25 01:29:09 +02:00
Dominik Sliwa
a60829b4cf USB-UART: PCB: Add CP2102n power diode and fix DRC issues
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-06-28 15:01:34 +02:00
Dominik Sliwa
04eb3ebc7e Adjust PoE and change 3.3V supply topology
-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-06-16 12:50:43 +02:00
Dominik Sliwa
5688e1d4e1 poe 1.3 improvements for emc includes MPS layout sugestions
decreased coupling between poe lines and  the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-06-13 23:20:13 +02:00
Stefan Agner
e0e2b8ecd0 Bump revision to 1.2
Bump revision to 1.2 in Schematic/PCB sheets and update the date.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-02-15 22:05:53 +01:00
Stefan Agner
37376dea76 Remove unused DRC exclusions
Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-02-15 21:59:48 +01:00
Dominik Sliwa
42cd10c86b Moved PoE few mm lower
In order to accomodate the C93 next to the transformer.
Added top layer GND1 pour under the transformer
shortened the GNDS path.

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 20:59:48 +01:00
Dominik Sliwa
9354729d76 Zone cleanup
Cleanup some fill zones.
Updated the Transformer symbol with pin 4, connected to +48V for better
zone fill.
fixed top/bottom transition for the DC_IN_F
Added some gnd vias

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 12:02:54 +01:00
Dominik Sliwa
8fd9133aec PoE EMI optimization
Modified PoE layout to account for GNDS-GND1 flow
and repositioned the noise retern capacitor.
Snubber was corrected for the transformer used and the switching
frequency. Some components were removed.
PoE Input filter was adjusted.

3.3 and 5V DCDC capacitor layout was optimised and unused components
were removed.

Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-02-15 00:29:21 +01:00
Dominik Sliwa
da1b852f0a Cleanup DRC violations
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
2022-01-10 08:59:52 +01:00
Stefan Agner
019c9efdda Rename Amber to Yellow everywhere
Signed-off-by: Stefan Agner <stefan@agner.ch>
2022-01-06 17:08:55 +01:00