Various BOM adjustments, most notably setting/correcting manufacturer
and part number information for D22, D30, FL1, L4 and L5.
Signed-off-by: Stefan Agner <stefan@agner.ch>
-eth shield is not connected to the GND rather it shields "input" of poe
-used smaller package for bulk PoE capacitor
-Changed common mode filter to Pulse T8113
-Added more inductor filters on the primary side
-replaced secondary side ferrite silter with an inductor
-used distributed "flyback" capacitor (3 instead of 1)
-slightly increased distance between the poe transformer and the
ethernet signal traces
- extended GND1 under the transformer
- primary snubber circuit is now in "hot-loop" area
-repositioned poe enable optocoupler
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
-Snubber circuit under ecrtail load condition can dissipate more power
then the resistor can handle, increased the resistor size and added one
more in parallel
-Increased size of some of the 12V input capacitors
-Use 3.3Vp instead of 3.3V generated by the RPi for LED, RTC, Radio, Fan
control and RPi reduced hat connector
-PoE pri/sec capacitor value changed
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
decreased coupling between poe lines and the gnd plane
added vias to stich main gnd planes
decreased the peak current through the transformer
inductor based pi filter on the poe output
decreased coupling to gnd of the poe "noise path"
added parallel mosfet capacitance to poe
moved fb line fo the dcdcs away from inductors
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Increment to sub-version v1.2. Main changes are:
- Back and front silk screen
- LED resistors
There are no changes in the layout and any critical components.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Fix edge cut on lower right corner to make board size exact
- Update board charactristics
- Set grid origin back to 30, 30
- Update M.2 expansion silk screen (remove AI accelerator hint)
- Various silk screen reference designator fixes/improvements
- Add ESD warning logo
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Update silk screen reference designators
- Update backside silk screen for Yellow revision 1.1
- Set U21 (SOIC-8 RTC) to assemble and U25 (MSOP-8) as DNP
- Update heatsink footprint to add heatsink outline to silk screen (#44)
- Mark orientation of D26, D27, D28 and D29 (fixes#39)
- Use pin-header footprint for PoE selector J13, it is now JP5
Signed-off-by: Stefan Agner <stefan@agner.ch>
-Fixed upstream diff pair polarity
-added optional inverer for the USB power switch enable pin
Design now supports both AP2181 and AP2191
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Run annotation again which just updated some net names. Address various
DRC issues like courtyard violence and exclude the remaining DRC errors.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- U7: Define Manufacturer/PartNumber
- J13: Define Manufacturer/PartNumber
- L2: Fix PartNumber (remove unprintable characters)
- C85: Change to our preferred supplier Nichicon
- J9: DNP (not used by default, avoid potential issues with FCC approval)
- Y1/Y2: Define frequency and load capacitance in value
- JP1: Use sensible part value
- C106: Fix Config field
- Remove heat sink and CM4 from BOM (handled in product assembly BOM)
Signed-off-by: Stefan Agner <stefan@agner.ch>
PoE
-Added a common mode filter on the input
-FB filter on the output side
-12V in now disables the poe with the DEN pin
-DT is now disabled
-PSRS is now disabled
-move to 1210 resistors for resistors identified in thermal testing
-DTHR is now enabled in default BoM
-some resistor values were adjusted
-some caps were moved to the common power supply section
USB:
-USB Hub 1.8V rail have capacitors added
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Update PCB from Schematics
- Move SD-card to bottom side of the PCB
- Place LEDs in front of CM4
- Add additional LEDs (Amber/Radio)
- Move LP5569 to the left
- Remove all holes
- Lock through holes which should not be moved
Fixes: #33
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Add Blue Radio LED (in a separate new assembly option)
- Change buffer package from SC-70 to SC-74A (aka. SOT-23-5)
- Add GND test point
Fixes: #31
Signed-off-by: Stefan Agner <stefan@agner.ch>
updates
schematic:
-change usb current protection IC to 1.5A
-Added low-pass filter to the audio output
-PoE fixed primary windings polarity
-added option to select poe class with a jumper (between 3 and 4)
-fixes in poe design
-added testpoints
-added virtual hirose df40c connectors for pick and place use
lightblue.pretty:
-added fake DF40C footprint for pick and place and 3d model purposes
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
- Add multiple ventilation slots (move some traces for space)
- Add Home Assistant logo to the back
- Add Nabu Casa logo on the front
- Fixup reference designators placement in several cases
Signed-off-by: Stefan Agner <stefan@agner.ch>
Order some relevant reference designator. Use JP for all jumpers. Place
silkcreen neatly. Add some custom silk screen. Remove heat sink corner
marks on silk screen.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Changes:
Footrints:
-Modified DC Jack to accomodate CUI PJ-002A
-Modified RJ45 to increase clearance between shield and poe pins
-Modified m.2 mounting pads to avoid drc errors
Schematic:
-usb-c facing usb mux is supplied by +3v3VP
-added misc. capacitors
PCB
-min. annular ring for vias set to 0.125 from 0.2
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Use JLC7628 impedance values to get more options in color selection.
Also this leads to slightly wider traces typically, and it will be
easier to switch back to JLC2313 or the like than the other way around.
Also swap placing of HDMI/SW2 and rotate the heatsink by 90° for easier
routing.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Adjust some high level placement like M.2 or CM4 and heatsink. Remove
all traces and vias since most of the layouting has to be redone
anyways.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Instead of using VBUS to power CP2102N use the main/NVMe 3.3V supply.
This makes sure that the device stays powered during reset, while making
sure the CP2102N is always powered and doesn't backfeed if no USB is
plugged in.
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Replace unusual/high value ceramics with lower value in parallel
- Use the same protection Shottky Diode in PoE as in regular input
(B340LB-13-F)
- Replace PoE rectifier Diodes with B1100-13-F
- Replace PoE Inductor (SRN6045TA-3R3Y) with the same part from 5V power
supply (Taiyo Yuden NRS8030T3R3MJGJ)
- Correctly specify Pulse Electronics transformer
Signed-off-by: Stefan Agner <stefan@agner.ch>
- Use Diodes B2100-13-F consistently
- Define part for pin headers
- Replace N-Channel MOSFET for PoE with BSZ440N10NS3GATMA1
- Define Input protection MOSFET DMP3013SFV-7
Signed-off-by: Stefan Agner <stefan@agner.ch>
Remove power/reset/recovery switch. Power and reset is not really required
and recovery mode (USB Boot) can be triggered via jumper. Make the Fan
and RPiLED a new separate config so we can leave them unpopulated. Add a
second GPIO controlled switch.
Fixes: #16
Signed-off-by: Stefan Agner <stefan@agner.ch>
Use a jumper instead of a switch to change between CM4 USB Device and
CP2102N. Replace CP2102N QFN24 with QFN20 variant. Make CP2102N to be
bus-powered by default.
Fixes: #7
Signed-off-by: Stefan Agner <stefan@agner.ch>
CRFILT capacitor is required for the chip to start properly
and 10k pull-downs were too strong according to the datasheet.
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
Add the CM4 board to board connectors using separate symbols. This is a
bit a hack, but makes sure two pieces appear in the BOM.
Also, this seems to upgrade all the schematic to the latest KiCad
schematic version.
Signed-off-by: Stefan Agner <stefan@agner.ch>
changes:
-more routing
-added poe negotiation disabled when +12V is present on the DC jack
-modified m.2 "holes"
Signed-off-by: Dominik Sliwa <dominik@sliwa.io>
