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59 Commits

Author SHA1 Message Date
David Given
56a36072f7 Sampler state machine cleanup; more debugging tools for the logic analyser. 2019-07-12 21:09:53 +02:00
David Given
1e3581c5f3 Turns out I was using the wrong error threshold flags for Mac disks. ND disks 
work fine now.
 2019-07-10 23:55:16 +02:00
David Given
7a775afaea Make sure that CounterClock is actually 12MHz, and not 12-ish MHz. Doesn't 
help.
 2019-07-10 20:26:17 +02:00
David Given
c27c4fe312 Synchronise input pins and set LVTTL levels. More correct, but doesn't help the 
read issues.
 2019-07-10 19:48:03 +02:00
David Given
ad295c683c The sampler pulse conversion now uses BUS_CLK as the sample clock. 2019-07-09 22:43:46 +02:00
David Given
98ea5e9600 Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser. 2019-07-08 01:08:05 +02:00
David Given
ce6077fa22 Apply Denis Kushch's timing fixes to the schematic. No more warnings on builds! 2019-07-08 00:52:59 +02:00
David Given
783b4fcf36 Switch the USB component to ask for 100mA rather than 500mA. 2019-04-21 01:18:28 +02:00
David Given
46b48f4638 Ignore the /DSKCHG line --- it doesn't add a lot of value (it allows us to 
rehome if people change disks while the motor is running) and it means that
people need to worry about whether their drive produces /DSKCHG or /READY.
 2019-04-21 01:15:30 +02:00
David Given
da8cae61b7 Add a debug UART back on pin 2.0 to get some semblance of debug information off 
the board. Discover a fun edge case where output transfers that were an exact
number of frames weren't being terminated correctly.
 2019-04-06 17:59:23 +02:00
David Given
bcc5a5f2cd Interim but working support for crunched data streams when reading from the 
device; writes haven't been converted yet. Reduces the bandiwidth from about
800kB/s to about 500kB/s, which is about what I thought.
 2019-03-26 23:03:19 +01:00
David Given
0453837c03 The high-density flag now actually changes the high-density line to the drive. 2019-03-26 20:05:16 +01:00
David Given
45eaf14133 Add a flag for setting the drive to high density mode. 2019-03-23 11:32:55 +01:00
David Given
4fe27afe9f Backed out changeset cd5bed99b0b4 --- erroneously pushed to master. 2019-03-24 17:59:17 +01:00
David Given
7f9a85ff77 Add a flag for setting the drive to high density mode. 2019-03-23 11:32:55 +01:00
David Given
29b66086ea The sequencer now (I hope, untested) supports waiting for the index hole. It's 
certainly no more non-functional than it was before, i.e. it writes Brother
disks fine.
 2019-03-07 00:10:12 +01:00
David Given
379985c2bc Rework the sampler state machine, with new, better, simpler bytecode at twice 
the bandwidth; we now record the state of the index hole.
 2019-03-06 21:09:07 +01:00
David Given
f20ad8368a Non-working basis of a UDB datapath based sequencer. No more clock errors. 2019-02-28 01:03:58 +01:00
David Given
6bcd9a6644 The UDB-based pulse generator is back. The problem was I was trying to write to 
a HD disk (also the logic was wrong). I think my new Sony drive doesn't
autoselect.
 2019-02-27 23:34:55 +01:00
David Given
b8138aef40 Replace the UDB based pulse generator with the old counter-based one, which 
seems to work.
 2019-02-27 23:18:19 +01:00
David Given
4b0c7b095b FINALLY make the UDB-based sampler work... although without rollover, yet. 
Sadly I seem to also have broken the sequencer.
 2019-02-27 23:00:47 +01:00
David Given
462d15369e Create a pulse generator UDB component --- hopefully cheaper than what we're currently doing. 2019-02-26 23:33:06 +01:00
David Given
039d6b5fdd More fiddling with the UDB sampler. Still doesn't work. 2019-02-26 22:37:45 +01:00
David Given
74c6c6db56 Non-working attempt at replacing the sampler with a UDB datapath (so I can use 
the FIFO).
 2019-02-24 14:50:33 +01:00
David Given
34a4c888b5 Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a 
little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
 2019-02-23 19:51:27 +01:00
David Given
753a4a21ef Rewrite the sampler Verilog to use much more consistent logic. Still doesn't 
work for long intervals, though.
 2019-02-23 12:42:42 +01:00
David Given
970668aca5 Non-working attempt to replace the playback logic with Verilog. 2019-02-22 21:26:54 +01:00
David Given
a77925fe64 Replace the complicated sampler with 10 lines of Verilog; the hardware should 
now be able to handle any length of transition. And it's simpler.
 2019-02-22 20:01:34 +01:00
David Given
2527ac2ce9 Initial support for twin drives and 5.25" drives. 2019-02-11 23:43:44 +01:00
David Given
65315f4603 Take out the UART --- it's too much hassle. 2019-02-09 23:02:05 +01:00
David Given
575213687e Move the pins to the other side of the board, so we don't need the capacitor 
hack any more.
 2019-02-09 22:50:43 +01:00
David Given
4f83aa8623 Change the USB ID to the new 1209:6e00 one allocated from pidcodes.github.com. 2018-12-14 19:08:19 +01:00
David Given
e6a424d17a Abruptly realise that the capture logic was completely missing transitions too 
big to time; so, redesign it. Now the longest transition is 0xfe ticks and a
pulse is inserted if it's too long. Capture is way more robust now and the
resulting pulsetrain is a solid 198ms; and I wrote my first readable disk! (A
PC HD disk. Sadly, writing to the Brother didn't work.)
 2018-10-17 00:26:33 +02:00
David Given
99e222d012 Change the record mechanism to use an upcounter, not a timer. 2018-10-13 16:54:51 +02:00
David Given
b46d55cc07 The USB capture/replay interface now uses timestamps rather than intervals; 
this makes the hardware considerably simpler and more reliable (as I don't need
to spend time resetting the timers between pulses). Still doesn't help writes,
though. Simplify and improve clock detection; add an abortive attempt at an FM
decoder (turns out that the Brother doesn't use FM).
 2018-10-13 01:19:17 +02:00
David Given
9dcfbc2ab1 More replay timer simplification: more robust? 2018-10-10 23:15:20 +02:00
David Given
1c0cc1f831 Rewrite the pulse replay logic to be, maybe, more reliable? Add lots of decoder 
debugging.
 2018-10-10 22:32:58 +02:00
David Given
40b9fbc25d Fix ghastly DMA ordering bug leading to corrupted writes. Writes are less 
corrupted! Still can't reliably read back what I wrote, though. Added a test
pattern feature to write, to aid debugging.
 2018-10-09 00:23:21 +02:00
David Given
443082f3c4 Written my first data --- it's kinda garbled, but there's definitely sectors in 
there!
 2018-10-06 23:30:14 +02:00
David Given
30271d7e95 Just enough writing works to utterly destroy tracks now. 2018-10-06 23:01:24 +02:00
David Given
8f1cef48b1 Realise that the weird data dropouts were due to a stray capacitor on the 
board... so remove it. Better now. Also realise that PSoC Creator lies to you
about clocks, so adjust the sample clock to be derivable from the USB clock,
making it both the right frequency and much more accurate --- decode success is
dramatically improved (presumably due to less jitter). Redesign the capture
logic to use a timer; simpler now.
 2018-10-06 18:32:57 +02:00
David Given
74d051dff3 Start sketching out the write code; attempt to make more robust in the face of 
the weird data dropouts.
 2018-10-06 13:47:34 +02:00
David Given
bf3e689708 Sketch out the replay logic, although it's not connected to anything yet. 2018-10-05 23:42:32 +02:00
David Given
d6b71beacf Reduced the sampling rate to 8MHz; 16MHz means that on a 720kB disk some 
samples are more than 128 ticks apart! Doubled the settling time to make reads
more reliable; added disk change logic to rehome the disk when you replace
floppies.
 2018-10-05 22:58:56 +02:00
David Given
339cdd5105 Add a partially working MFM decoder --- MFM's fine, it's aligning to sync bytes 
which is hard.
 2018-10-04 00:02:13 +02:00
David Given
fccabb3266 Add back in the hacky output file, for testing; replace the capture logic with 
an upcounter, and replace the pulse-in-high-bit stuff.
 2018-10-03 19:45:27 +02:00
David Given
a8738915e9 You can now read complete disk images into a database file. 2018-10-03 00:03:50 +02:00
David Given
841c1ed516 Attempt to capture rollover events --- don't think it works. Add a basic 
command processor.
 2018-10-02 23:03:07 +02:00
David Given
913829afbb Discover timers; drastically simplify and betterify everything. 2018-10-02 00:17:37 +02:00
David Given
51cb1ae785 We just read our first floppy! Turns out the secret is to, once again, remove 
C7 from the board as it's preventing the READ DATA line showing anything.
 2018-10-01 23:30:51 +02:00