David Given
a9e30c1e49
Fix an off-by-one error in the sequencer that should have it generating correct
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sequences.
2020-04-03 22:58:51 +02:00
David Given
0644d6d965
Remove some stray tracing (which was causing problems). Fix a potential problem
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where sampleclock posedges could be lost in the sequencer.
2020-03-29 23:11:53 +02:00
David Given
a075694d8e
Rewrite the sequencer to work with the new six bit bytecode. Fiddle with the
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USB stuff a lot in an attempt to resolve the weird packet loss issue.
2020-03-29 15:10:35 +02:00
David Given
edc56d44d6
Non-functioning archive checkin: You can only have 120-odd DMA buffers, so my
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last 'fix' was in fact non-functional.
2020-02-17 23:28:40 +01:00
David Given
ef4eff0195
So writing now works, but only if USB DMA is enabled. But that breaks reading.
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I've worked round this in a simple but brute force manner and it now looks as
if reading *and* writing work, more or less. There does still seem to be the
odd bad sector when writing 1440kB disks.
2020-02-17 21:41:01 +01:00
David Given
df8d45bf66
Rework the output fifo to be a bit more correct about the sync signals, which
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in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.
2020-02-17 00:13:13 +01:00
David Given
b448ab7917
Finally squeeze everything in to the Verilog sampler. It does seem to work
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better... the the USB hangup problem persists. Mac disks are still
nigh-unreadable.
2019-12-12 00:12:20 +01:00
David Given
1e012699af
Clean up the Verilog a bit.
2019-11-25 20:54:13 +01:00
David Given
91d6e9aeb9
Rewrite the sequencer engine with a separate fifo component and a pure verilog
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sequencer --- much easier to understand. We can write disks again!
2019-11-25 20:52:13 +01:00
David Given
1d6f112b53
Remove the old logic-based sequencer.
2019-02-28 21:29:01 +01:00
David Given
462d15369e
Create a pulse generator UDB component --- hopefully cheaper than what we're currently doing.
2019-02-26 23:33:06 +01:00
David Given
34a4c888b5
Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a
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little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
2019-02-23 19:51:27 +01:00
David Given
753a4a21ef
Rewrite the sampler Verilog to use much more consistent logic. Still doesn't
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work for long intervals, though.
2019-02-23 12:42:42 +01:00
David Given
6a1327e3f6
Attempt to translate the sequencer into Verilog and have it handle long
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intervals properly.
2019-02-23 00:50:36 +01:00
