Merge pull request #118 from davidgiven/fixing

Fix a few minor build tweaks.
This works; final tweaking.
2025-10-24 11:11:02 -07:00 · 2019-12-13 23:56:12 +01:00 · 2019-12-13 23:53:42 +01:00 · 2019-12-13 23:50:33 +01:00 · 2019-12-13 23:48:17 +01:00 · 2019-12-13 23:45:17 +01:00
46 changed files with 3748 additions and 2551 deletions
--- a/.github/workflows/ccpp.yml
+++ b/.github/workflows/ccpp.yml
@@ -0,0 +1,34 @@
+name: C/C++ CI
+
+on: [push]
+
+jobs:
+  build-linux:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: apt
+      run: sudo apt install libusb-1.0-0-dev libsqlite3-dev ninja-build
+    - name: make
+      run: make
+
+  build-macos:
+    runs-on: macos-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: brew
+      run: brew install sqlite pkg-config libusb ninja
+    - name: make
+      run: make
+
+#  build-windows:
+#    runs-on: windows-latest
+#    steps:
+#    - uses: numworks/setup-msys2@v1
+#      with:
+#        msystem: MSYS
+#    - uses: actions/checkout@v1
+#    - name: pacman
+#      run: msys2do pacman -S --noconfirm --needed make ninja mingw-w64-i686-libusb mingw-w64-i686-sqlite3 mingw-w64-i686-zlib mingw-w64-i686-gcc zip
+#    - name: make
+#      run: msys2do make
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,39 +0,0 @@
-language: shell
-git:
-    depth: 1
-
-matrix:
-    include:
-        -
-            os: linux
-            sudo: false
-            dist: xenial
-            compiler: gcc
-            env: CXX=g++-8
-            script:
-            - make
-        -
-            os: osx
-            osx_image: xcode10.2
-            compiler: clang
-            env:
-            - HOMEBREW_NO_INSTALL_CLEANUP=1
-
-addons:
-    apt:
-        sources:
-        - llvm-toolchain-precise-3.8
-        - ubuntu-toolchain-r-test
-        packages:
-        - ninja-build
-        - libusb-1.0-0-dev
-        - libsqlite3-dev
-        - g++-8
-    homebrew:
-        packages:
-        - ninja
-
-script:
- make
-
-
--- a/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
+++ b/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
@@ -1,244 +1,244 @@
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@@ -4615,12 +4615,12 @@
 :0200000490105A
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 :0200000490501A
-:0C00000000012E16106900002E2A5C83FF
+:0C00000000012E16106900002E317F96C2
 :00000001FF
--- a/FluxEngine.cydsn/FIFOin/API/c.c
+++ b/FluxEngine.cydsn/FIFOin/API/c.c
@@ -0,0 +1,27 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}
--- a/FluxEngine.cydsn/FIFOin/API/h.h
+++ b/FluxEngine.cydsn/FIFOin/API/h.h
@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOin/FIFOin.cysym
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.cysym
--- a/FluxEngine.cydsn/FIFOin/FIFOin.v
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.v
@@ -0,0 +1,128 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+
+/* Ultra-simple FIFO in component: a byte is shifted in every clock when req
+ * is high. */
+ 
+module FIFOin (drq, clk, d, req);
+	output  drq;
+	input   clk;
+	input  [7:0] d;
+	input  req;
+
+//`#start body` -- edit after this line, do not edit this line
+
+wire [7:0] pi;
+assign pi = d;
+
+wire load;
+assign load = req;
+
+cy_psoc3_dp #(.cy_dpconfig(
+{
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM0:    */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM1:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM2:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM3:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM4:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM5:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM6:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM7:     */
+	8'hFF, 8'h00,	/*CFG9:     */
+	8'hFF, 8'hFF,	/*CFG11-10:     */
+	`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+	`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+	`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+	`SC_SI_A_DEFSI, /*CFG13-12:     */
+	`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
+	1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
+	`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+	`SC_FB_NOCHN, `SC_CMP1_NOCHN,
+	`SC_CMP0_NOCHN, /*CFG15-14:     */
+	10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+	`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
+	`SC_WRK16CAT_DSBL /*CFG17-16:     */
+}
+)) dp(
+	/* input          */ .clk(clk),
+	/* input [02:00]  */ .cs_addr(3'b0),    // Program counter
+	/* input          */ .route_si(1'b0),   // Shift in
+	/* input          */ .route_ci(1'b0),   // Carry in
+	/* input          */ .f0_load(load),    // Load FIFO 0
+	/* input          */ .f1_load(1'b0), 	// Load FIFO 1
+	/* input          */ .d0_load(1'b0), 	// Load Data Register 0
+	/* input          */ .d1_load(1'b0), 	// Load Data Register 1
+	/* output         */ .ce0(), 			// Accumulator 0 = Data register 0
+	/* output         */ .cl0(), 			// Accumulator 0 < Data register 0
+	/* output         */ .z0(), 			// Accumulator 0 = 0
+	/* output         */ .ff0(), 			// Accumulator 0 = FF
+	/* output         */ .ce1(), 			// Accumulator [0|1] = Data register 1
+	/* output         */ .cl1(), 			// Accumulator [0|1] < Data register 1
+	/* output         */ .z1(), 			// Accumulator 1 = 0
+	/* output         */ .ff1(), 			// Accumulator 1 = FF
+	/* output         */ .ov_msb(), 		// Operation over flow
+	/* output         */ .co_msb(), 		// Carry out
+	/* output         */ .cmsb(), 			// Carry out
+	/* output         */ .so(), 			// Shift out
+    /* output         */ .f0_bus_stat(drq), // not empty
+	/* output         */ .f0_blk_stat(full),// full
+	/* output         */ .f1_bus_stat(), 	// FIFO 1 status to uP
+	/* output         */ .f1_blk_stat(), 	// FIFO 1 status to DP
+	/* input          */ .ci(1'b0), 		// Carry in from previous stage
+	/* output         */ .co(), 			// Carry out to next stage
+	/* input          */ .sir(1'b0), 		// Shift in from right side
+	/* output         */ .sor(), 			// Shift out to right side
+	/* input          */ .sil(1'b0), 		// Shift in from left side
+	/* output         */ .sol(), 			// Shift out to left side
+	/* input          */ .msbi(1'b0), 		// MSB chain in
+	/* output         */ .msbo(), 			// MSB chain out
+	/* input [01:00]  */ .cei(2'b0),        // Compare equal in from prev stage
+	/* output [01:00] */ .ceo(),            // Compare equal out to next stage
+	/* input [01:00]  */ .cli(2'b0), 	    // Compare less than in from prv stage
+	/* output [01:00] */ .clo(),            // Compare less than out to next stage
+	/* input [01:00]  */ .zi(2'b0),         // Zero detect in from previous stage
+	/* output [01:00] */ .zo(),             // Zero detect out to next stage
+	/* input [01:00]  */ .fi(2'b0), 		// 0xFF detect in from previous stage
+	/* output [01:00] */ .fo(), 	        // 0xFF detect out to next stage
+	/* input [01:00]  */ .capi(2'b0),	    // Capture in from previous stage
+	/* output [01:00] */ .capo(),		    // Capture out to next stage
+	/* input          */ .cfbi(1'b0), 		// CRC Feedback in from previous stage
+	/* output         */ .cfbo(), 			// CRC Feedback out to next stage
+	/* input [07:00]  */ .pi(pi), 		    // Parallel data port
+	/* output [07:00] */ .po()              // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
--- a/FluxEngine.cydsn/FIFOout/API/c.c
+++ b/FluxEngine.cydsn/FIFOout/API/c.c
@@ -0,0 +1,27 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}
--- a/FluxEngine.cydsn/FIFOout/API/h.h
+++ b/FluxEngine.cydsn/FIFOout/API/h.h
@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOout/FIFOout.cysym
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.cysym
--- a/FluxEngine.cydsn/FIFOout/FIFOout.v
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.v
@@ -0,0 +1,168 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module FIFOout (
+    input req,
+	input clk,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+/* Reads from the FIFO are done based on the FIFO being not empty. */
+ 
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_WAIT = 1'b0;
+localparam STATE_READ = 1'b1;
+
+reg state;
+reg oldreq;
+
+assign ack = (state != STATE_READ);
+
+always @(posedge clk)
+begin
+    case (state)
+        STATE_WAIT:
+        begin
+            if (!empty)
+            begin
+                if (req && !oldreq)
+                begin
+                    state <= STATE_READ;
+                end
+                oldreq <= req;
+            end
+        end
+        
+        STATE_READ:
+        begin
+            state <= STATE_WAIT;
+        end
+    endcase
+end
+            
+cy_psoc3_dp #(.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:           */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:           */
+    8'hFF, 8'h00,  /*CFG9:           */
+    8'hFF, 8'hFF,  /*CFG11-10:           */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:           */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:           */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:           */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr({2'b0, state}),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(drq), // not full
+        /*  output                  */  .f0_blk_stat(empty), // empty
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
--- a/FluxEngine.cydsn/FluxEngine.cydwr
+++ b/FluxEngine.cydsn/FluxEngine.cydwr
@@ -28,6 +28,54 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_5" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_5" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_8" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -147,6 +195,54 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="71bc291d-84a7-40a8-b7b2-1c8a34326a31">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="300" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK300" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK300" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="90ce0c72-9f10-44ef-a049-f0f525d59bea">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="128" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK8" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="349ffa20-8576-4ac3-9a6f-34ef606de6cf">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -170,6 +266,29 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="OUTPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\OUTPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="6616e828-6611-4893-a674-66c861d79d6c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -241,6 +360,53 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="09974428-e912-491f-8d2f-361ba50e7599">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_6" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_6" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="INPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\INPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="b762c287-7f87-4b21-982e-84be01dc5115">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -288,6 +454,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="b722443b-8f81-46dc-bf9b-c95eb62bc181">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_1" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_1" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -312,6 +502,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_7" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_7" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="e4a53a4c-40e1-4747-a72a-10193ffdf31c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -609,18 +823,27 @@
  <Group key="DWRInstGuidMapping">
    <Group key="Clock">
      <Data key="0b2f9bbb-00ce-4115-a788-ffb9d046a9e5" value="Clock_4" />
+      <Data key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b" value="Clock_5" />
+      <Data key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2" value="Clock_8" />
      <Data key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4" value="Clock_3" />
      <Data key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec" value="CounterClock" />
      <Data key="24cd38f7-f472-4403-837f-86807c8f5333" value="PULSE_CLOCK" />
      <Data key="63ed4137-0b09-4256-8a27-35c9a2653f1a" value="Clock_2" />
      <Data key="66f14071-bddd-4b4d-a9aa-a129cceaa7b6" value="Clock_3" />
+      <Data key="71bc291d-84a7-40a8-b7b2-1c8a34326a31" value="CLOCK300" />
+      <Data key="90ce0c72-9f10-44ef-a049-f0f525d59bea" value="CLOCK8" />
      <Data key="349ffa20-8576-4ac3-9a6f-34ef606de6cf" value="Clock_1" />
+      <Data key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a" value="OUTPUT_VOLTAGE_ADC_theACLK" />
      <Data key="6616e828-6611-4893-a674-66c861d79d6c" value="SignalSamplingClock" />
      <Data key="12664fc6-9d70-44b1-8a49-887a292e1b7f" value="Clock_3" />
      <Data key="75187c05-9501-4450-b306-6ccdd3bb77db" value="Clock_5" />
+      <Data key="09974428-e912-491f-8d2f-361ba50e7599" value="Clock_6" />
+      <Data key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a" value="INPUT_VOLTAGE_ADC_theACLK" />
      <Data key="b762c287-7f87-4b21-982e-84be01dc5115" value="Clock_2" />
      <Data key="b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358" value="UART_IntClock" />
+      <Data key="b722443b-8f81-46dc-bf9b-c95eb62bc181" value="Clock_1" />
      <Data key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c" value="CounterClock" />
+      <Data key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f" value="Clock_7" />
      <Data key="e4a53a4c-40e1-4747-a72a-10193ffdf31c" value="Clock_1" />
      <Data key="efd5f185-0c32-4824-ba72-3ceb5356f5a7" value="Clock_1" />
    </Group>
@@ -638,16 +861,18 @@
      <Data key="a5d987c6-e45b-45b9-ad93-656fab06d720" value="TRK00" />
      <Data key="a93ef5b3-00f4-42c0-8fad-0e275a7e2537" value="MOTEB" />
      <Data key="b8380fb7-fdb8-449f-bd8d-c4ca96cdf55a" value="DEBUG_PINS" />
+      <Data key="bc2e8987-db82-469c-bf6f-22fd3464cc70" value="DEBUG_PINS" />
      <Data key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f" value="DEBUG_PINS" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c" value="USBFS_Dm" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42" value="USBFS_Dp" />
      <Data key="c5367cde-21d5-4866-9a32-d16abfea0c61" value="WPT" />
      <Data key="d19368c5-6855-41bb-a9ff-808938abef00" value="INDEX" />
      <Data key="e9f14b5a-b2bf-49b8-98f3-d7b5a43ace8d" value="DRVSB" />
-      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED" />
+      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="INDEX300" />
      <Data key="e51063a9-4fad-40c7-a06b-7cc4b137dc18" value="DSKCHG" />
      <Data key="ea7ee228-8b3f-426c-8bb8-cd7a81937769" value="DIR" />
      <Data key="ed092b9b-d398-4703-be89-cebf998501f6" value="UartTx" />
+      <Data key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663" value="INDEX360" />
      <Data key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="UART_tx" />
      <Data key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b" value="DRVSA" />
      <Data key="fff78075-035e-43d7-8577-bc5be4d21926" value="WGATE" />
@@ -3859,6 +4084,32 @@
        <Data key="Port Format" value="2,3" />
      </Group>
    </Group>
+    <Group key="bc2e8987-db82-469c-bf6f-22fd3464cc70">
+      <Group key="0">
+        <Data key="Port Format" value="0,0" />
+      </Group>
+      <Group key="1">
+        <Data key="Port Format" value="0,1" />
+      </Group>
+      <Group key="2">
+        <Data key="Port Format" value="0,2" />
+      </Group>
+      <Group key="3">
+        <Data key="Port Format" value="0,3" />
+      </Group>
+      <Group key="4">
+        <Data key="Port Format" value="0,4" />
+      </Group>
+      <Group key="5">
+        <Data key="Port Format" value="0,5" />
+      </Group>
+      <Group key="6">
+        <Data key="Port Format" value="0,6" />
+      </Group>
+      <Group key="7">
+        <Data key="Port Format" value="0,7" />
+      </Group>
+    </Group>
    <Group key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f">
      <Group key="0">
        <Data key="Port Format" value="0,5" />
@@ -3894,7 +4145,7 @@
    </Group>
    <Group key="e851a3b9-efb8-48be-bbb8-b303b216c393">
      <Group key="0">
-        <Data key="Port Format" value="2,1" />
+        <Data key="Port Format" value="3,0" />
      </Group>
    </Group>
    <Group key="e51063a9-4fad-40c7-a06b-7cc4b137dc18">
@@ -3912,9 +4163,14 @@
        <Data key="Port Format" value="12,7" />
      </Group>
    </Group>
+    <Group key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663">
+      <Group key="0">
+        <Data key="Port Format" value="3,1" />
+      </Group>
+    </Group>
    <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
      <Group key="0">
-        <Data key="Port Format" value="2,5" />
+        <Data key="Port Format" value="12,7" />
      </Group>
    </Group>
    <Group key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b">
--- a/FluxEngine.cydsn/FluxEngine.cyprj
+++ b/FluxEngine.cydsn/FluxEngine.cyprj
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
--- a/FluxEngine.cydsn/Sampler/Sampler.v
+++ b/FluxEngine.cydsn/Sampler/Sampler.v
@@ -0,0 +1,134 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+`include "../SuperCounter/SuperCounter.v"
+
+//`#end` -- edit above this line, do not edit this line
+// Generated on 12/11/2019 at 21:18
+// Component: Sampler
+module Sampler (
+	output [2:0] debug_state,
+	output reg [7:0] opcode,
+	output  req,
+	input   clock,
+	input   index,
+	input   rdata,
+	input   reset,
+	input   sampleclock
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_RESET = 0;
+localparam STATE_WAITING = 1;
+localparam STATE_INTERVAL = 2;
+localparam STATE_DISPATCH = 3;
+localparam STATE_OPCODE = 4;
+localparam STATE_COUNTING = 5;
+
+reg [2:0] state;
+wire [6:0] counter;
+
+wire countnow;
+assign countnow = (state == STATE_COUNTING);
+
+wire counterreset;
+assign counterreset = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+SuperCounter #(.Delta(1), .ResetValue(0)) Counter
+(
+    /* input */ .clk(clock),
+    /* input */ .reset(counterreset),
+    /* input */ .count(countnow),
+    /* output */ .d(counter)
+);
+
+reg oldsampleclock;
+wire sampleclocked;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+assign indexed = !oldindex && index;
+
+wire rdataed;
+reg oldrdata;
+assign rdataed = !oldrdata && rdata;
+
+assign req = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_RESET;
+        opcode <= 0;
+        oldsampleclock <= 0;
+        oldindex <= 0;
+        oldrdata <= 0;
+    end
+    else
+        case (state)
+            STATE_RESET:
+                state <= STATE_WAITING;
+            
+            STATE_WAITING:
+            begin
+                if (rdataed || indexed)
+                begin
+                    opcode <= {0, counter};
+                    state <= STATE_INTERVAL;
+                end
+                else if (sampleclocked)
+                begin
+                    oldsampleclock <= 1;
+                    if (counter == 7'h7f)
+                    begin
+                        opcode <= {0, counter};
+                        state <= STATE_OPCODE;
+                    end
+                    else
+                        state <= STATE_COUNTING;
+                end
+                
+                if (oldrdata && !rdata)
+                    oldrdata <= 0;
+                if (oldindex && !index)
+                    oldindex <= 0;
+                if (oldsampleclock && !sampleclock)
+                    oldsampleclock <= 0;
+            end
+            
+            STATE_INTERVAL: /* interval byte sent here; counter reset */
+                state <= STATE_DISPATCH;
+                
+            STATE_DISPATCH: /* relax after interval byte, dispatch for opcode */
+            begin
+                if (rdataed)
+                begin
+                    oldrdata <= 1;
+                    opcode <= 8'h80;
+                    state <= STATE_OPCODE;
+                end
+                else if (indexed)
+                begin
+                    oldindex <= 1;
+                    opcode <= 8'h81;
+                    state <= STATE_OPCODE;
+                end
+                else
+                    state <= STATE_WAITING;
+            end
+            
+            STATE_OPCODE: /* opcode byte sent here */
+                state <= STATE_WAITING;
+                            
+            STATE_COUNTING:
+                state <= STATE_WAITING;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
--- a/FluxEngine.cydsn/Sequencer/Sequencer.v
+++ b/FluxEngine.cydsn/Sequencer/Sequencer.v
@@ -0,0 +1,103 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/24/2019 at 17:25
+// Component: Sequencer
+module Sequencer (
+	output req, /* request new data on leading edge */
+	output wdata,
+    output [2:0] debug_state,
+	input clock,
+	input dataclock, /* incoming data on leading edge */
+	input [7:0] opcode,
+    input index,
+    input sampleclock,
+    input reset
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_IDLE = 0;
+localparam STATE_LOAD = 1;
+localparam STATE_WAITING = 2;
+localparam STATE_PULSING = 3;
+localparam STATE_INDEXING = 4;
+
+localparam OPCODE_PULSE = 8'h80;
+localparam OPCODE_INDEX = 8'h81;
+
+reg [2:0] state;
+reg [6:0] countdown;
+
+assign req = (state == STATE_LOAD);
+assign wdata = (state == STATE_PULSING);
+assign debug_state = state;
+
+reg olddataclock;
+wire dataclocked;
+always @(posedge clock) olddataclock <= dataclock;
+assign dataclocked = !olddataclock && dataclock;
+
+reg oldsampleclock;
+wire sampleclocked;
+always @(posedge clock) oldsampleclock <= sampleclock;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+always @(posedge clock) oldindex <= index;
+assign indexed = !oldindex && index;
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_IDLE;
+        countdown <= 0;
+    end
+    else
+        case (state)
+            STATE_IDLE:
+                state <= STATE_LOAD;
+            
+            STATE_LOAD:
+                if (dataclocked)
+                    case (opcode)
+                        OPCODE_PULSE:
+                            state <= STATE_PULSING;
+                        
+                        OPCODE_INDEX:
+                            state <= STATE_INDEXING;
+                        
+                        default:
+                        begin
+                            countdown <= opcode[6:0];
+                            state <= STATE_WAITING;
+                        end
+                    endcase
+            
+            STATE_WAITING:
+                if (sampleclocked)
+                begin
+                    if (countdown == 0)
+                        state <= STATE_LOAD;
+                    else
+                        countdown <= countdown - 1;
+                end
+            
+            STATE_PULSING:
+                state <= STATE_LOAD;
+            
+            STATE_INDEXING:
+                if (indexed)
+                    state <= STATE_LOAD;
+                else
+                    state <= STATE_INDEXING;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.v
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.v
@@ -0,0 +1,156 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module SuperCounter (
+	input clk,
+    input reset,
+    input count,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+parameter ResetValue = 0;
+parameter Delta = 1;
+    
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_RESET = 0;
+localparam STATE_WAIT = 1;
+localparam STATE_ADD = 2;
+
+reg oldcount;
+wire counted;
+assign counted = count && !oldcount;
+
+always @(posedge clk) oldcount <= count;
+
+wire [2:0] cs;
+assign cs = reset ? STATE_RESET : (counted ? STATE_ADD : STATE_WAIT);
+            
+cy_psoc3_dp #(.d0_init(ResetValue), .d1_init(Delta), 
+.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0:  STATE_RESET*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1:  STATE_WAIT*/
+    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D1,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:  STATE_ADD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:             */
+    8'hFF, 8'h00,  /*CFG9:             */
+    8'hFF, 8'hFF,  /*CFG11-10:             */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:             */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:             */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:             */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr(cs),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(),
+        /*  output                  */  .f0_blk_stat(),
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- a/FluxEngine.cydsn/TopDesign/TopDesign.cysch
+++ b/FluxEngine.cydsn/TopDesign/TopDesign.cysch
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
--- a/FluxEngine.cydsn/main.c
+++ b/FluxEngine.cydsn/main.c
@@ -85,10 +85,21 @@ static void print(const char* msg, ...)
    UART_PutCRLF();
 }

+static void set_drive_flags(uint8_t flags)
+{
+    if (current_drive_flags != flags)
+        homed = false;
+    
+    current_drive_flags = flags;
+    DRIVESELECT_REG_Write((flags & 1) ? 2 : 1); /* select drive 1 or 0 */
+    DENSITY_REG_Write(flags >> 1); /* density bit */
+}
+
 static void start_motor(void)
 {
    if (!motor_on)
    {
+        set_drive_flags(current_drive_flags);
        MOTOR_REG_Write(1);
        CyDelay(1000);
        homed = false;
@@ -99,6 +110,16 @@ static void start_motor(void)
    CyWdtClear();
 }

+static void stop_motor(void)
+{
+    if (motor_on)
+    {
+        MOTOR_REG_Write(0);
+        DRIVESELECT_REG_Write(0); /* deselect all drives */
+        motor_on = false;
+    }
+}
+
 static void wait_until_writeable(int ep)
 {
    while (USBFS_GetEPState(ep) != USBFS_IN_BUFFER_EMPTY)
@@ -138,25 +159,36 @@ static void cmd_get_version(struct any_frame* f)

 static void step(int dir)
 {
-    STEP_REG_Write(dir);
-    CyDelayUs(1);
-    STEP_REG_Write(dir | 2);
-    CyDelayUs(1);
-    STEP_REG_Write(dir);
+    STEP_REG_Write(dir); /* step high */
+    CyDelayUs(6);
+    STEP_REG_Write(dir | 2); /* step low */
+    CyDelayUs(6);
+    STEP_REG_Write(dir); /* step high again, drive moves now */
    CyDelay(STEP_INTERVAL_TIME);
 }

+static void home(void)
+{
+    for (int i=0; i<100; i++)
+    {
+        /* Don't keep stepping forever, because if a drive's
+         * not connected bad things happen. */
+        if (TRACK0_REG_Read())
+            break;
+        step(STEP_TOWARDS0);
+    }
+    
+    /* Step to -1, which should be a nop, to reset the disk on disk change. */
+    step(STEP_TOWARDS0);
+}
+
 static void seek_to(int track)
 {
    start_motor();
-    if (!homed)
+    if (!homed || (track == 0))
    {
        print("homing");
-        while (!TRACK0_REG_Read())
-            step(STEP_TOWARDS0);
-            
-        /* Step to -1, which should be a nop, to reset the disk on disk change. */
-        step(STEP_TOWARDS0);
+        home();
        
        homed = true;
        current_track = 0;
@@ -167,11 +199,7 @@ static void seek_to(int track)
    while (track != current_track)
    {
        if (TRACK0_REG_Read())
-        {
-            if (current_track != 0)
-                print("unexpectedly detected track 0");
            current_track = 0;
-        }
        
        if (track > current_track)
        {
@@ -249,7 +277,7 @@ static void deinit_dma(void)

 static void init_capture_dma(void)
 {
-    dma_channel = CAPTURE_DMA_DmaInitialize(
+    dma_channel = SAMPLER_DMA_DmaInitialize(
        2 /* bytes */,
        true /* request per burst */, 
        HI16(CYDEV_PERIPH_BASE),
@@ -264,8 +292,8 @@ static void init_capture_dma(void)
            nexti = 0;

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],   
-            CY_DMA_TD_INC_DST_ADR | CAPTURE_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&SAMPLER_DATAPATH_F0_REG), LO16((uint32)&dma_buffer[i]));
+            CY_DMA_TD_INC_DST_ADR | SAMPLER_DMA__TD_TERMOUT_EN);
+        CyDmaTdSetAddress(td[i], LO16((uint32)SAMPLER_FIFO_FIFO_PTR), LO16((uint32)&dma_buffer[i]));
    }    
 }

@@ -276,13 +304,11 @@ static void cmd_read(struct read_frame* f)
    
    /* Do slow setup *before* we go into the real-time bit. */
    
-    SAMPLER_CONTROL_Write(1); /* reset */
-    
    {
        uint8_t i = CyEnterCriticalSection();
-        SAMPLER_DATAPATH_F0_SET_LEVEL_MID;
-        SAMPLER_DATAPATH_F0_CLEAR;
-        SAMPLER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        SAMPLER_FIFO_SET_LEVEL_MID;
+        SAMPLER_FIFO_CLEAR;
+        SAMPLER_FIFO_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    
@@ -291,7 +317,6 @@ static void cmd_read(struct read_frame* f)

    /* Wait for the beginning of a rotation. */
        
-    print("wait");
    index_irq = false;
    while (!index_irq)
        ;
@@ -305,8 +330,6 @@ static void cmd_read(struct read_frame* f)
    dma_reading_from_td = -1;
    dma_underrun = false;
    int count = 0;
-    SAMPLER_CONTROL_Write(0); /* !reset */
-    CAPTURE_CONTROL_Write(1);
    CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
    CyDmaClearPendingDrq(dma_channel);
    CyDmaChEnable(dma_channel, 1);
@@ -366,19 +389,20 @@ static void cmd_read(struct read_frame* f)
        dma_reading_from_td = NEXT_BUFFER(dma_reading_from_td);
    }
 abort:;
-    CAPTURE_CONTROL_Write(0);
    CyDmaChSetRequest(dma_channel, CY_DMA_CPU_TERM_CHAIN);
    while (CyDmaChGetRequest(dma_channel))
        ;

    donecrunch(&cs);
    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
-    unsigned zz = cs.outputlen;
-    if (cs.outputlen != BUFFER_SIZE)
-        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+    if (!dma_underrun)
+    {
+        if (cs.outputlen != BUFFER_SIZE)
+            USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+        wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
+    }
    if ((cs.outputlen == BUFFER_SIZE) || (cs.outputlen == 0))
        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, NULL, 0);
-    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
    deinit_dma();

    if (dma_underrun)
@@ -391,7 +415,7 @@ abort:;
        DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_READ_REPLY);
        send_reply(&r);
    }
-    print("count=%d i=%d d=%d zz=%d", count, index_irq, dma_underrun, zz);
+    print("count=%d i=%d d=%d", count, index_irq, dma_underrun);
 }

 static void init_replay_dma(void)
@@ -412,25 +436,28 @@ static void init_replay_dma(void)

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],
            CY_DMA_TD_INC_SRC_ADR | SEQUENCER_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)&SEQUENCER_DATAPATH_F0_REG));
+        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)REPLAY_FIFO_FIFO_PTR));
    }    
 }

 static void cmd_write(struct write_frame* f)
 {
+    print("cmd_write");
+    
    if (f->bytes_to_write % FRAME_SIZE)
    {
        send_error(F_ERROR_INVALID_VALUE);
        return;
    }
    
+    SEQUENCER_CONTROL_Write(1); /* put the sequencer into reset */
+
    SIDE_REG_Write(f->side);
-    SEQUENCER_CONTROL_Write(1); /* reset */
    {
-        uint8_t i = CyEnterCriticalSection();
-        SEQUENCER_DATAPATH_F0_SET_LEVEL_NORMAL;
-        SEQUENCER_DATAPATH_F0_CLEAR;
-        SEQUENCER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        uint8_t i = CyEnterCriticalSection();        
+        REPLAY_FIFO_SET_LEVEL_NORMAL;
+        REPLAY_FIFO_CLEAR;
+        REPLAY_FIFO_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    seek_to(current_track);    
@@ -555,7 +582,7 @@ abort:
        CyDmaChDisable(dma_channel);
    }
    
-    //debug("p=%d cr=%d cw=%d f=%d l=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, listening, writing, index_irq, dma_underrun);
+    print("p=%d cr=%d cw=%d f=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, writing, index_irq, dma_underrun);
    if (!finished)
    {
        while (count_read < packets)
@@ -573,6 +600,7 @@ abort:
    }
    
    deinit_dma();
+    print("write finished");
    
    if (dma_underrun)
    {
@@ -607,17 +635,101 @@ static void cmd_erase(struct erase_frame* f)

 static void cmd_set_drive(struct set_drive_frame* f)
 {
-    if (current_drive_flags != f->drive_flags)
-    {
-        current_drive_flags = f->drive_flags;
-        DRIVE_REG_Write(current_drive_flags);
-        homed = false;
-    }
+    set_drive_flags(f->drive_flags);
    
    DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_SET_DRIVE_REPLY);
    send_reply((struct any_frame*) &r);
 }
-   
+
+static uint16_t read_output_voltage_mv(void)
+{
+    OUTPUT_VOLTAGE_ADC_StartConvert();
+    OUTPUT_VOLTAGE_ADC_IsEndConversion(OUTPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
+    uint16_t samples = OUTPUT_VOLTAGE_ADC_GetResult16();
+    return OUTPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
+}
+
+static void read_output_voltages(struct voltages* v)
+{
+    SIDE_REG_Write(1); /* set DIR to low (remember this is inverted) */
+    CyDelay(100);
+    v->logic0_mv = read_output_voltage_mv();
+
+    SIDE_REG_Write(0);
+    CyDelay(100);
+    v->logic1_mv = read_output_voltage_mv();
+}
+
+static uint16_t read_input_voltage_mv(void)
+{
+    INPUT_VOLTAGE_ADC_StartConvert();
+    INPUT_VOLTAGE_ADC_IsEndConversion(INPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
+    uint16_t samples = INPUT_VOLTAGE_ADC_GetResult16();
+    return INPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
+}
+
+static void read_input_voltages(struct voltages* v)
+{
+    home();
+    CyDelay(50);
+    v->logic0_mv = read_input_voltage_mv();
+    
+    step(STEP_AWAYFROM0);
+    CyDelay(50);
+    v->logic1_mv = read_input_voltage_mv();
+}
+
+static void cmd_measure_voltages(void)
+{
+    stop_motor();
+    INPUT_VOLTAGE_ADC_Start();
+    INPUT_VOLTAGE_ADC_SetPower(INPUT_VOLTAGE_ADC__HIGHPOWER);
+    OUTPUT_VOLTAGE_ADC_Start();
+    OUTPUT_VOLTAGE_ADC_SetPower(OUTPUT_VOLTAGE_ADC__HIGHPOWER);
+    
+    DECLARE_REPLY_FRAME(struct voltages_frame, F_FRAME_MEASURE_VOLTAGES_REPLY);
+    
+    CyWdtClear();
+    MOTOR_REG_Write(0); /* should be ignored anyway */
+    DRIVESELECT_REG_Write(0); /* deselect both drives */
+    CyDelay(200); /* wait for things to settle */
+    read_output_voltages(&r.output_both_off);
+    read_input_voltages(&r.input_both_off);
+
+    CyWdtClear();
+    DRIVESELECT_REG_Write(1); /* select drive 0 */
+    CyDelay(50);
+    read_output_voltages(&r.output_drive_0_selected);
+    read_input_voltages(&r.input_drive_0_selected);
+    MOTOR_REG_Write(1);
+    CyDelay(300);
+    CyWdtClear();
+    read_output_voltages(&r.output_drive_0_running);
+    read_input_voltages(&r.input_drive_0_running);
+    MOTOR_REG_Write(0);
+    CyDelay(300);
+    
+    CyWdtClear();
+    DRIVESELECT_REG_Write(2); /* select drive 1 */
+    CyDelay(50);
+    read_output_voltages(&r.output_drive_1_selected);
+    read_input_voltages(&r.input_drive_1_selected);
+    MOTOR_REG_Write(1);
+    CyDelay(300);
+    CyWdtClear();
+    read_output_voltages(&r.output_drive_1_running);
+    read_input_voltages(&r.input_drive_1_running);
+    MOTOR_REG_Write(0);
+    CyDelay(300);
+
+    CyWdtClear();
+    DRIVESELECT_REG_Write(0);
+    homed = false;
+    INPUT_VOLTAGE_ADC_Stop();
+    OUTPUT_VOLTAGE_ADC_Stop();
+    send_reply((struct any_frame*) &r);
+}
+
 static void handle_command(void)
 {
    static uint8_t input_buffer[FRAME_SIZE];
@@ -662,6 +774,10 @@ static void handle_command(void)
        case F_FRAME_SET_DRIVE_CMD:
            cmd_set_drive((struct set_drive_frame*) f);
            break;
+        
+        case F_FRAME_MEASURE_VOLTAGES_CMD:
+            cmd_measure_voltages();
+            break;
            
        default:
            send_error(F_ERROR_BAD_COMMAND);
@@ -674,9 +790,11 @@ int main(void)
    CySysTickStart();
    CySysTickSetCallback(4, system_timer_cb);
    INDEX_IRQ_StartEx(&index_irq_cb);
-    CAPTURE_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
+    SAMPLER_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
    SEQUENCER_DMA_FINISHED_IRQ_StartEx(&replay_dma_finished_irq_cb);
-    DRIVE_REG_Write(0);
+    INPUT_VOLTAGE_ADC_Stop();
+    OUTPUT_VOLTAGE_ADC_Stop();
+    DRIVESELECT_REG_Write(0);
    UART_Start();
    USBFS_Start(0, USBFS_DWR_VDDD_OPERATION);
    
@@ -692,10 +810,7 @@ int main(void)
        {
            uint32_t time_on = clock - motor_on_time;
            if (time_on > MOTOR_ON_TIME)
-            {
-                MOTOR_REG_Write(0);
-                motor_on = false;
-            }
+                stop_motor();
        }
        
        if (!USBFS_GetConfiguration() || USBFS_IsConfigurationChanged())
@@ -709,6 +824,7 @@ int main(void)
        
        if (USBFS_GetEPState(FLUXENGINE_CMD_OUT_EP_NUM) == USBFS_OUT_BUFFER_FULL)
        {
+            set_drive_flags(current_drive_flags);
            handle_command();
            USBFS_EnableOutEP(FLUXENGINE_CMD_OUT_EP_NUM);
            print("idle");
--- a/7
+++ b/7
@@ -13,6 +13,13 @@ export LDFLAGS +=
 export LIBS = -static -lz -lsqlite3 -lusb-1.0
 export EXTENSION = .exe
 else
+
+packages-exist = $(shell pkg-config --exists $(PACKAGES) && echo yes)
+ifneq ($(packages-exist),yes)
+$(warning These pkg-config packages are installed: $(shell pkg-config --list-all | sort | awk '{print $$1}'))
+$(error You must have these pkg-config packages installed: $(PACKAGES))
+endif
+
 export CXX = g++
 export AR = ar rcs
 export STRIP = strip
--- a/README.md
+++ b/README.md
@@ -89,7 +89,7 @@ people who've had it work).
 | [Brother 120kB](doc/disk-brother.md)     |  🦄   |        |                                     |
 | [Brother 240kB](doc/disk-brother.md)     |  🦄   |   🦄   |                                     |
 | [Brother FB-100](doc/disk-fb100.md)      |  🦖   |        | Tandy Model 100, Husky Hunter, knitting machines |
-| [Macintosh 800kB](doc/disk-macintosh.md) |  🦄   |        | and probably the 400kB too          |
+| [Macintosh 800kB](doc/disk-macintosh.md) |  🦖   |        | and probably the 400kB too          |
 | [TRS-80](doc/disk-trs80.md)              |  🦖   |        | a minor variation of the IBM scheme |
 {: .datatable }

--- a/doc/Index_sensor_mod_FDD_1.1.pdf
+++ b/doc/Index_sensor_mod_FDD_1.1.pdf
--- a/doc/disk-brother.md
+++ b/doc/disk-brother.md
@@ -129,8 +129,8 @@ reverse engineered it to find out.

 Standard Linux mtools will access the filesystem image and allow you to move
 files in and out. However, you'll need to change the media type bytes at
-offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. Once
-done, this will work:
+offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. The
+supplied `brother240tool` will do this. Once done, this will work:

 ```
 mdir -i brother.img
--- a/doc/disk-macintosh.md
+++ b/doc/disk-macintosh.md
@@ -28,8 +28,16 @@ for example the Commodore 64 1541 drive, changed bitrate this way.
 But Macintosh disks used a constant bitrate and changed the speed that the
 disk spun instead to achieve the same effect...

-_Anyway_: FluxEngine will read them fine on a conventional drive. Because
-it's clever.
+_Anyway_: FluxEngine will read them fine on conventional drives.
+Because it's clever.
+
+**Big note.** Apparently --- and I'm still getting to the bottom of this ---
+some drives work and some don't. My drives produce about 90% good reads of
+known good disks. One rumour I've heard is that drives sometimes include
+filters which damage the signals at very particular intervals which Mac disks
+use, but frankly this seems unlikely; it could be a software issue at my end
+and I'm investigating. If you have any insight, please [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).

 Reading discs
 -------------
--- a/doc/faq.md
+++ b/doc/faq.md
@@ -48,7 +48,7 @@ haven't had the chance to try it end-for-end. I really need a hard-sectored

 **Q.** Does it work with flippy disks?

-Uhhh... probably not.
+Uhhh... maybe?

 So the problem with flippy disks (5.25" single-sided disks which could be
 inserted upside down to read the second side) is the index hole. Trouble is,
@@ -79,16 +79,21 @@ the other. But a flippy disk has both sets of tracks in the same place,
 because they're both accessed using the side 0 head...

 The only real way round this is to modify a 5.25" drive. That's _seriously_
-not in FluxEngine's remit. Sorry.
+not in FluxEngine's remit, but I've had some [excellent documentation
+contributed](Index_sensor_mod_FDD_1.1.pdf) on how to do this. I've never done
+it myself; if you try this and it works/doesn't work, as always, [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).

-**Q.** Is this like KryoFlux / Catweasel / DiskFerret? Do you support KryoFlux
+**Q.** Is this like Supercard Pro / KryoFlux / Catweasel / DiskFerret? Do you
+*support KryoFlux
 stream files?

 **A.** It's very like all of these; the idea's old, and lots of people have
 tried it (you can get away with any sufficiently fast microcontroller and
 enough RAM). FluxEngine can read from KryoFlux stream files natively, and
-there's a tool which will let you convert at least one kind of Catweasel file
-to FluxEngine's native flux file format.
+there's a tool which will let you convert at least one kind of Catweasel
+files and Supercard Pro files to and from FluxEngine's native flux file
+format.

 **Q.** Can I use this to make exact copies of disks?

--- a/doc/technical.md
+++ b/doc/technical.md
@@ -123,8 +123,12 @@ admittedly expensive.)
    sheet](http://www.bitsavers.org/pdf/mitsubishi/floppy/M4851/TJ2-G30211A_M4851_DSHH_48TPI_OEM_Manual_Nov83.pdf):
    the equivalent data sheet for a representative 5.25" drive.

+  - [The DRG Business Machines YD-174 manual](https://electrickery.hosting.philpem.me.uk/comp/divcomp/doc/YE_Data_YD-174_8inchFloppyDriveTechnicalManual.pdf):
+	the equivalent manual (data sheets hadn't been invented then) for a
+	representative 8" drive.
+
  - [KryoFlux stream file
    documentation](https://www.kryoflux.com/download/kryoflux_stream_protocol_rev1.1.pdf):
    the format of KryoFlux stream files (partially supported by FluxEngine)

-  
+  
--- a/doc/using.md
+++ b/doc/using.md
@@ -51,7 +51,7 @@ In order to do anything useful, you have to plug it in to a floppy disk drive (o
     rpm for a 3.5" disk, or 360 rpm for a 5.25" disk. If it doesn't, please
     [get in touch](https://github.com/davidgiven/fluxengine/issues/new).

-  7. Do `fluxengine testbulktransport` from the shell. It'll measure your USB
+  7. Do `fluxengine test bulktransport` from the shell. It'll measure your USB
     bandwidth. Ideally you should be getting above 900kB/s. FluxEngine needs
     about 850kB/s, so if you're getting less than this, try a different USB
     port.
@@ -213,19 +213,30 @@ directory.
  - `fluxengine seek`: moves the head. Mainly useful for finding out whether
  your drive can seek to track 82. (Mine can't.)

-  - `fluxengine testbulktransport`: measures your USB throughput. You need
+  - `fluxengine test bulktransport`: measures your USB throughput. You need
  about 600kB/s for FluxEngine to work. You don't need a disk in the drive
  for this one.

+  - `fluxengine test voltages`: measures your FDD bus signal voltages, which
+  is useful for testing for termination issues.
+
  - `fluxengine upgradefluxfile`: occasionally I need to upgrade the flux
  file format in a non-backwards-compatible way; this tool will upgrade flux
  files to the new format.

-  - `fluxengine convert`: converts various formats to various other formats.
-  You can use this to convert Catweasel or Supercard Pro flux files to
-  FluxEngine's native format, for flux files to various other formats useful
-  for debugging (including VCD which can be loaded into
-  [sigrok](http://sigrok.org)).
+  - `fluxengine convert`: converts flux files from various formats to various
+  other formats. You can use this to convert Catweasel flux files to
+  FluxEngine's native format, FluxEngine flux files to various other formats
+  useful for debugging (including VCD which can be loaded into
+  [sigrok](http://sigrok.org)), and bidirectional conversion to and from
+  Supercard Pro `.scp` format.
+
+  **Important SCP note:** import (`fluxengine convert scptoflux`) should be
+  fairly robust, but export (`fluxengine convert fluxtoscp`) should only be
+  done with great caution as FluxEngine files contain features which can't be
+  represented very well in `.scp` format and they're probably pretty dubious.
+  As ever, please [get in
+  touch](https://github.com/davidgiven/fluxengine/issues/new) with any reports.

 Commands which normally take `--source` or `--dest` get a sensible default if
 left unspecified. `fluxengine read ibm` on its own will read drive 0 and
--- a/lib/flags.cc
+++ b/lib/flags.cc
@@ -29,7 +29,7 @@ void FlagGroup::addFlag(Flag* flag)
    _flags.push_back(flag);
 }

-void FlagGroup::parseFlags(int argc, const char* argv[])
+std::vector<std::string> FlagGroup::parseFlagsWithFilenames(int argc, const char* argv[])
 {
    if (_initialised)
        throw std::runtime_error("called parseFlags() twice");
@@ -66,6 +66,7 @@ void FlagGroup::parseFlags(int argc, const char* argv[])

    /* Now actually parse them. */

+    std::vector<std::string> filenames;
    int index = 1;
    while (index < argc)
    {
@@ -76,52 +77,73 @@ void FlagGroup::parseFlags(int argc, const char* argv[])
        std::string value;
        bool usesthat = false;

-        if ((thisarg.size() == 0) || (thisarg[0] != '-'))
-            Error() << "non-option parameter " << thisarg << " seen (try --help)";
-        if ((thisarg.size() > 1) && (thisarg[1] == '-'))
+        if (thisarg.size() == 0)
        {
-            /* Long option. */
-
-            auto equals = thisarg.rfind('=');
-            if (equals != std::string::npos)
-            {
-                key = thisarg.substr(0, equals);
-                value = thisarg.substr(equals+1);
-            }
-            else
-            {
-                key = thisarg;
-                value = thatarg;
-                usesthat = true;
-            }
+            /* Ignore this argument. */
+        }
+        else if (thisarg[0] != '-')
+        {
+            /* This is a filename. */
+            filenames.push_back(thisarg);
        }
        else
        {
-            /* Short option. */
+            /* This is a flag. */

-            if (thisarg.size() > 2)
+            if ((thisarg.size() > 1) && (thisarg[1] == '-'))
            {
-                key = thisarg.substr(0, 2);
-                value = thisarg.substr(2);
+                /* Long option. */
+
+                auto equals = thisarg.rfind('=');
+                if (equals != std::string::npos)
+                {
+                    key = thisarg.substr(0, equals);
+                    value = thisarg.substr(equals+1);
+                }
+                else
+                {
+                    key = thisarg;
+                    value = thatarg;
+                    usesthat = true;
+                }
            }
            else
            {
-                key = thisarg;
-                value = thatarg;
-                usesthat = true;
+                /* Short option. */
+
+                if (thisarg.size() > 2)
+                {
+                    key = thisarg.substr(0, 2);
+                    value = thisarg.substr(2);
+                }
+                else
+                {
+                    key = thisarg;
+                    value = thatarg;
+                    usesthat = true;
+                }
            }
+
+            auto flag = flags_by_name.find(key);
+            if (flag == flags_by_name.end())
+                Error() << "unknown flag '" << key << "'; try --help";
+
+            flag->second->set(value);
+            if (usesthat && flag->second->hasArgument())
+                index++;
        }

-        auto flag = flags_by_name.find(key);
-        if (flag == flags_by_name.end())
-            Error() << "unknown flag '" << key << "'; try --help";
-
-        flag->second->set(value);
-
        index++;
-        if (usesthat && flag->second->hasArgument())
-            index++;
    }
+
+    return filenames;
+}
+
+void FlagGroup::parseFlags(int argc, const char* argv[])
+{
+    auto filenames = parseFlagsWithFilenames(argc, argv);
+    if (!filenames.empty())
+        Error() << "non-option parameter " << *filenames.begin() << " seen (try --help)";
 }

 void FlagGroup::checkInitialised() const
--- a/lib/flags.h
+++ b/lib/flags.h
@@ -14,6 +14,7 @@ public:

 public:
    void parseFlags(int argc, const char* argv[]);
+    std::vector<std::string> parseFlagsWithFilenames(int argc, const char* argv[]);
    void addFlag(Flag* flag);
    void checkInitialised() const;

--- a/lib/usb.cc
+++ b/lib/usb.cc
@@ -265,3 +265,37 @@ void usbSetDrive(int drive, bool high_density)
    await_reply<struct any_frame>(F_FRAME_SET_DRIVE_REPLY);
 }

+/* Hacky: the board always operates in little-endian mode. */
+static uint16_t read_short_from_usb(uint16_t usb)
+{
+    uint8_t* p = (uint8_t*)&usb;
+    return p[0] | (p[1] << 8);
+}
+
+static void convert_voltages_from_usb(const struct voltages& vin, struct voltages& vout)
+{
+    vout.logic0_mv = read_short_from_usb(vin.logic0_mv);
+    vout.logic1_mv = read_short_from_usb(vin.logic1_mv);
+}
+
+void usbMeasureVoltages(struct voltages_frame* voltages)
+{
+    usb_init();
+
+    struct any_frame f = {
+        { .type = F_FRAME_MEASURE_VOLTAGES_CMD, .size = sizeof(f) },
+    };
+    usb_cmd_send(&f, f.f.size);
+
+    struct voltages_frame* r = await_reply<struct voltages_frame>(F_FRAME_MEASURE_VOLTAGES_REPLY);
+    convert_voltages_from_usb(r->input_both_off, voltages->input_both_off);
+    convert_voltages_from_usb(r->input_drive_0_selected, voltages->input_drive_0_selected);
+    convert_voltages_from_usb(r->input_drive_1_selected, voltages->input_drive_1_selected);
+    convert_voltages_from_usb(r->input_drive_0_running, voltages->input_drive_0_running);
+    convert_voltages_from_usb(r->input_drive_1_running, voltages->input_drive_1_running);
+    convert_voltages_from_usb(r->output_both_off, voltages->output_both_off);
+    convert_voltages_from_usb(r->output_drive_0_selected, voltages->output_drive_0_selected);
+    convert_voltages_from_usb(r->output_drive_1_selected, voltages->output_drive_1_selected);
+    convert_voltages_from_usb(r->output_drive_0_running, voltages->output_drive_0_running);
+    convert_voltages_from_usb(r->output_drive_1_running, voltages->output_drive_1_running);
+}
--- a/lib/usb.h
+++ b/lib/usb.h
@@ -13,5 +13,6 @@ extern Bytes usbRead(int side, int revolutions);
 extern void usbWrite(int side, const Bytes& bytes);
 extern void usbErase(int side);
 extern void usbSetDrive(int drive, bool high_density);
+extern void usbMeasureVoltages(struct voltages_frame* voltages);

 #endif
--- a/mkninja.sh
+++ b/mkninja.sh
@@ -190,6 +190,7 @@ buildlibrary libfrontend.a \
    src/fe-cwftoflux.cc \
    src/fe-erase.cc \
    src/fe-fluxtoau.cc \
+    src/fe-fluxtoscp.cc \
    src/fe-fluxtovcd.cc \
    src/fe-inspect.cc \
    src/fe-readadfs.cc \
@@ -211,6 +212,7 @@ buildlibrary libfrontend.a \
    src/fe-scptoflux.cc \
    src/fe-seek.cc \
    src/fe-testbulktransport.cc \
+    src/fe-testvoltages.cc \
    src/fe-upgradefluxfile.cc \
    src/fe-writebrother.cc \
    src/fe-writeflux.cc \
@@ -232,6 +234,13 @@ buildsimpleprogram brother120tool \
    libemu.a \
    libfmt.a \

+buildsimpleprogram brother240tool \
+	-Idep/emu \
+    tools/brother240tool.cc \
+    libbackend.a \
+    libemu.a \
+    libfmt.a \
+
 runtest bitaccumulator-test tests/bitaccumulator.cc
 runtest bytes-test          tests/bytes.cc
 runtest compression-test    tests/compression.cc
--- a/protocol.h
+++ b/protocol.h
@@ -62,6 +62,8 @@ enum
    F_FRAME_RECALIBRATE_REPLY,    /* any_frame */
    F_FRAME_SET_DRIVE_CMD,        /* setdrive_frame */
    F_FRAME_SET_DRIVE_REPLY,      /* any_frame */
+    F_FRAME_MEASURE_VOLTAGES_CMD, /* any_frame */
+    F_FRAME_MEASURE_VOLTAGES_REPLY, /* voltages_frame */
 };

 enum
@@ -146,4 +148,25 @@ struct set_drive_frame
    uint8_t drive_flags;
 };

+struct voltages
+{
+    uint16_t logic0_mv;
+    uint16_t logic1_mv;
+};
+
+struct voltages_frame
+{
+    struct frame_header f;
+    struct voltages output_both_off;
+    struct voltages output_drive_0_selected;
+    struct voltages output_drive_1_selected;
+    struct voltages output_drive_0_running;
+    struct voltages output_drive_1_running;
+    struct voltages input_both_off;
+    struct voltages input_drive_0_selected;
+    struct voltages input_drive_1_selected;
+    struct voltages input_drive_0_running;
+    struct voltages input_drive_1_running;
+};
+
 #endif
--- a/src/fe-erase.cc
+++ b/src/fe-erase.cc
@@ -3,7 +3,7 @@
 #include "fluxmap.h"
 #include "writer.h"

-static FlagGroup flags;
+static FlagGroup flags { &writerFlags };

 int mainErase(int argc, const char* argv[])
 {
--- a/src/fe-fluxtoscp.cc
+++ b/src/fe-fluxtoscp.cc
@@ -0,0 +1,188 @@
+#include "globals.h"
+#include "flags.h"
+#include "fluxmap.h"
+#include "sql.h"
+#include "bytes.h"
+#include "protocol.h"
+#include "dataspec.h"
+#include "fmt/format.h"
+#include "decoders/fluxmapreader.h"
+#include "scp.h"
+#include <fstream>
+#include <algorithm>
+
+static FlagGroup flags { };
+
+static SettableFlag fortyTrackMode(
+    { "--48", "-4" },
+    "set 48 tpi mode; only every other physical track is emitted"
+);
+
+static SettableFlag singleSided(
+    { "--single-sided", "-s" },
+    "only emit side 0"
+);
+
+static IntFlag diskType(
+    { "--disk-type" },
+    "sets the SCP disk type byte",
+    0xff
+);
+
+static sqlite3* inputDb;
+
+static void syntax()
+{
+    std::cout << "Syntax: fluxengine convert fluxtoscp <fluxfile> <scpfile>\n";
+    exit(0);
+}
+
+static void write_le32(uint8_t dest[4], uint32_t v)
+{
+    dest[0] = v;
+    dest[1] = v >> 8;
+    dest[2] = v >> 16;
+    dest[3] = v >> 24;
+}
+
+static int strackno(int track, int side)
+{
+    if (fortyTrackMode)
+        track /= 2;
+    if (singleSided)
+        return track;
+    else
+        return (track << 1) | side;
+}
+
+int mainConvertFluxToScp(int argc, const char* argv[])
+{
+    auto filenames = flags.parseFlagsWithFilenames(argc, argv);
+    if (filenames.size() != 2)
+        syntax();
+
+    inputDb = sqlOpen(filenames[0], SQLITE_OPEN_READONLY);
+    auto tracks = sqlFindFlux(inputDb);
+
+    int maxTrack = 0;
+    int maxSide = 0;
+    for (auto p : tracks)
+    {
+        if (singleSided && (p.second == 1))
+            continue;
+        maxTrack = std::max(maxTrack, (int)p.first);
+        maxSide = std::max(maxSide, (int)p.second);
+    }
+    int maxStrack = strackno(maxTrack, maxSide);
+
+    std::cout << fmt::format("Writing {} {} SCP file containing {} SCP tracks\n",
+        fortyTrackMode ? "48 tpi" : "96 tpi",
+        singleSided ? "single sided" : "double sided",
+        maxStrack + 1
+    );
+
+    ScpHeader fileheader = {0};
+    fileheader.file_id[0] = 'S';
+    fileheader.file_id[1] = 'C';
+    fileheader.file_id[2] = 'P';
+    fileheader.version = 0x18; /* Version 1.8 of the spec */
+    fileheader.type = diskType;
+    fileheader.revolutions = 5;
+    fileheader.start_track = 0;
+    fileheader.end_track = maxStrack;
+    fileheader.flags = SCP_FLAG_INDEXED | (fortyTrackMode ? 0 : SCP_FLAG_96TPI);
+    fileheader.cell_width = 0;
+    fileheader.heads = singleSided ? 1 : 0;
+
+    Bytes trackdata;
+    ByteWriter trackdataWriter(trackdata);
+
+    int trackstep = 1 + fortyTrackMode;
+    int maxside = singleSided ? 0 : 1;
+    for (int track = 0; track <= maxTrack; track += trackstep)
+    {
+        for (int side = 0; side <= maxside; side++)
+        {
+            int strack = strackno(track, side);
+            std::cout << fmt::format("FE track {}.{}, SCP track {}: ", track, side, strack) << std::flush;
+
+            auto fluxmap = sqlReadFlux(inputDb, track, side);
+            ScpTrack trackheader = {0};
+            trackheader.track_id[0] = 'T';
+            trackheader.track_id[1] = 'R';
+            trackheader.track_id[2] = 'K';
+            trackheader.strack = strack;
+
+            FluxmapReader fmr(*fluxmap);
+            Bytes fluxdata;
+            ByteWriter fluxdataWriter(fluxdata);
+
+            int revolution = 0;
+            unsigned revTicks = 0;
+            unsigned totalTicks = 0;
+            unsigned ticksSinceLastPulse = 0;
+            uint32_t startOffset = 0;
+            while (revolution < 5)
+            {
+                unsigned ticks;
+                int opcode = fmr.readOpcode(ticks);
+                if (ticks)
+                {
+                    ticksSinceLastPulse += ticks;
+                    totalTicks += ticks;
+                    revTicks += ticks;
+                }
+
+                switch (opcode)
+                {
+                    case -1: /* end of flux, treat like an index marker */
+                    case F_OP_INDEX:
+                    {
+                        auto* revheader = &trackheader.revolution[revolution];
+                        write_le32(revheader->offset, startOffset + sizeof(ScpTrack));
+                        write_le32(revheader->length, (fluxdataWriter.pos - startOffset) / 2);
+                        write_le32(revheader->index, revTicks * NS_PER_TICK / 25);
+                        revolution++;
+                        revheader++;
+                        revTicks = 0;
+                        startOffset = fluxdataWriter.pos;
+                        break;
+                    }
+
+                    case F_OP_PULSE:
+                    {
+                        unsigned t = ticksSinceLastPulse * NS_PER_TICK / 25;
+                        while (t >= 0x10000)
+                        {
+                            fluxdataWriter.write_be16(0);
+                            t -= 0x10000;
+                        }
+                        fluxdataWriter.write_be16(t);
+                        ticksSinceLastPulse = 0;
+                        break;
+                    }
+                }
+            }
+
+            write_le32(fileheader.track[strack], trackdataWriter.pos + sizeof(ScpHeader));
+            trackdataWriter += Bytes((uint8_t*)&trackheader, sizeof(trackheader));
+            trackdataWriter += fluxdata;
+
+            std::cout << fmt::format("{} ms in {} bytes\n",
+                totalTicks * MS_PER_TICK,
+                fluxdata.size());
+        }
+    }
+
+    sqlClose(inputDb);
+    
+    std::cout << "Writing output file...\n";
+    std::ofstream of(filenames[1], std::ios::out | std::ios::binary);
+    if (!of.is_open())
+        Error() << "cannot open output file";
+    of.write((const char*) &fileheader, sizeof(fileheader));
+    of.write((const char*) trackdata.begin(), trackdata.size());
+    of.close();
+
+    return 0;
+}
--- a/src/fe-readmx.cc
+++ b/src/fe-readmx.cc
@@ -8,7 +8,6 @@
 #include "sector.h"
 #include "sectorset.h"
 #include "record.h"
-#include <fmt/format.h>

 static FlagGroup flags { &readerFlags };

--- a/src/fe-rpm.cc
+++ b/src/fe-rpm.cc
@@ -8,7 +8,7 @@ static FlagGroup flags;
 static DataSpecFlag source(
    { "--source", "-s" },
    "source for data",
-    ":d=0");
+    ":d=0:t=0:s=0");

 int mainRpm(int argc, const char* argv[])
 {
--- a/src/fe-scptoflux.cc
+++ b/src/fe-scptoflux.cc
@@ -4,37 +4,9 @@
 #include "bytes.h"
 #include "protocol.h"
 #include "fmt/format.h"
+#include "scp.h"
 #include <fstream>

-struct ScpHeader
-{
-    char file_id[3];       // file ID - 'SCP'
-    uint8_t version;       // major/minor in nibbles
-    uint8_t type;          // disk type - subclass/class in nibbles
-    uint8_t revolutions;   // up to 5
-    uint8_t start_track;   // 0..165
-    uint8_t end_track;     // 0..165
-    uint8_t flags;         // see below
-    uint8_t cell_width;    // in bits, 0 meaning 16
-    uint8_t heads;         // 0 = both, 1 = side 0 only, 2 = side 1 only
-    uint8_t resolution;    // 25ns * (resolution+1)
-    uint8_t checksum[4];   // of data after this point
-    uint8_t track[165][4]; // track offsets, not necessarily 165
-};
-
-struct ScpTrack
-{
-    char track_id[3];      // 'TRK'
-    uint8_t strack;        // SCP track number
-    struct
-    {
-        uint8_t index[4];  // time for one revolution
-        uint8_t length[4]; // number of bitcells
-        uint8_t offset[4]; // offset to bitcell data, relative to track header
-    }
-    revolution[5];
-};
-
 static std::ifstream inputFile;
 static sqlite3* outputDb;
 static ScpHeader header;
@@ -109,6 +81,7 @@ static void read_track(int strack)

    Fluxmap fluxmap;
    nanoseconds_t pending = 0;
+    unsigned inputBytes = 0;
    for (int revolution = 0; revolution < header.revolutions; revolution++)
    {
        if (revolution != 0)
@@ -133,12 +106,14 @@ static void read_track(int strack)
                pending = 0;
            }
            else
-                pending += interval;
+                pending += 0x10000;
        }
+
+        inputBytes += datalength*2;
    }

-    std::cout << fmt::format(" {} ms in {} output bytes\n",
-        fluxmap.duration() / 1e6, fluxmap.bytes());
+    std::cout << fmt::format(" {} ms in {} input bytes and {} output bytes\n",
+        fluxmap.duration() / 1e6, inputBytes, fluxmap.bytes());
    sqlWriteFlux(outputDb, trackno(strack), headno(strack), fluxmap);
 }

--- a/src/fe-testvoltages.cc
+++ b/src/fe-testvoltages.cc
@@ -0,0 +1,47 @@
+#include "globals.h"
+#include "flags.h"
+#include "usb.h"
+#include "protocol.h"
+#include <fmt/format.h>
+
+static FlagGroup flags;
+
+static std::string display_voltages(struct voltages& v)
+{
+    return fmt::format(
+        "      Logic 1 / 0:  {:.2f}V / {:.2f}V\n",
+        v.logic0_mv / 1000.0,
+        v.logic1_mv / 1000.0);
+}
+
+int mainTestVoltages(int argc, const char* argv[])
+{
+    flags.parseFlags(argc, argv);
+    struct voltages_frame f;
+    usbMeasureVoltages(&f);
+
+    std::cout << "Output voltages:\n"
+              << "  Both drives deselected\n"
+              << display_voltages(f.output_both_off)
+              << "  Drive 0 selected\n"
+              << display_voltages(f.output_drive_0_selected)
+              << "  Drive 1 selected\n"
+              << display_voltages(f.output_drive_1_selected)
+              << "  Drive 0 running\n"
+              << display_voltages(f.output_drive_0_running)
+              << "  Drive 1 running\n"
+              << display_voltages(f.output_drive_1_running)
+              << "Input voltages:\n"
+              << "  Both drives deselected\n"
+              << display_voltages(f.input_both_off)
+              << "  Drive 0 selected\n"
+              << display_voltages(f.input_drive_0_selected)
+              << "  Drive 1 selected\n"
+              << display_voltages(f.input_drive_1_selected)
+              << "  Drive 0 running\n"
+              << display_voltages(f.input_drive_0_running)
+              << "  Drive 1 running\n"
+              << display_voltages(f.input_drive_1_running);
+
+    return 0;
+}
--- a/src/fluxengine.cc
+++ b/src/fluxengine.cc
@@ -5,6 +5,7 @@ typedef int command_cb(int agrc, const char* argv[]);
 extern command_cb mainErase;
 extern command_cb mainConvertCwfToFlux;
 extern command_cb mainConvertFluxToAu;
+extern command_cb mainConvertFluxToScp;
 extern command_cb mainConvertFluxToVcd;
 extern command_cb mainConvertScpToFlux;
 extern command_cb mainInspect;
@@ -26,6 +27,7 @@ extern command_cb mainReadZilogMCZ;
 extern command_cb mainRpm;
 extern command_cb mainSeek;
 extern command_cb mainTestBulkTransport;
+extern command_cb mainTestVoltages;
 extern command_cb mainUpgradeFluxFile;
 extern command_cb mainWriteBrother;
 extern command_cb mainWriteFlux;
@@ -41,6 +43,7 @@ struct Command
 static command_cb mainRead;
 static command_cb mainWrite;
 static command_cb mainConvert;
+static command_cb mainTest;

 static std::vector<Command> commands =
 {
@@ -50,7 +53,7 @@ static std::vector<Command> commands =
    { "read",              mainRead,              "Reads a disk, producing a sector image.", },
    { "rpm",               mainRpm,               "Measures the disk rotational speed.", },
    { "seek",              mainSeek,              "Moves the disk head.", },
-    { "testbulktransport", mainTestBulkTransport, "Measures your USB bandwidth.", },
+    { "test",              mainTest,              "Various testing commands.", },
    { "upgradefluxfile",   mainUpgradeFluxFile,   "Upgrades a flux file from a previous version of this software.", },
    { "write",             mainWrite,             "Writes a sector image to a disk.", },
    { "writeflux",         mainWriteFlux,         "Writes a raw flux file. Warning: you can't use this to copy disks.", },
@@ -86,9 +89,16 @@ static std::vector<Command> convertables =
    { "cwftoflux",     mainConvertCwfToFlux, "Converts CatWeasel stream files to flux.", },
    { "scptoflux",     mainConvertScpToFlux, "Converts Supercard Pro stream files to flux.", },
    { "fluxtoau",      mainConvertFluxToAu,  "Converts (one track of a) flux file to an .au audio file.", },
+    { "fluxtoscp",     mainConvertFluxToScp, "Converrt a flux file to a Supercard Pro file.", },
    { "fluxtovcd",     mainConvertFluxToVcd, "Converts (one track of a) flux file to a VCD file.", },
 };

+static std::vector<Command> testables =
+{
+    { "bulktransport", mainTestBulkTransport, "Measures your USB bandwidth.", },
+    { "voltages",      mainTestVoltages,      "Measures the FDD bus voltages.", },
+};
+
 static void extendedHelp(std::vector<Command>& subcommands, const std::string& command)
 {
    std::cout << "fluxengine: syntax: fluxengine " << command << " <format> [<flags>...]\n"
@@ -129,6 +139,9 @@ static int mainWrite(int argc, const char* argv[])
 static int mainConvert(int argc, const char* argv[])
 { return mainExtended(convertables, "convert", argc, argv); }

+static int mainTest(int argc, const char* argv[])
+{ return mainExtended(testables, "test", argc, argv); }
+
 static void help()
 {
    std::cout << "fluxengine: syntax: fluxengine <command> [<flags>...]\n"
--- a/src/scp.h
+++ b/src/scp.h
@@ -0,0 +1,43 @@
+#ifndef SCP_H
+#define SCP_H
+
+struct ScpHeader
+{
+    char file_id[3];       // file ID - 'SCP'
+    uint8_t version;       // major/minor in nibbles
+    uint8_t type;          // disk type - subclass/class in nibbles
+    uint8_t revolutions;   // up to 5
+    uint8_t start_track;   // 0..165
+    uint8_t end_track;     // 0..165
+    uint8_t flags;         // see below
+    uint8_t cell_width;    // in bits, 0 meaning 16
+    uint8_t heads;         // 0 = both, 1 = side 0 only, 2 = side 1 only
+    uint8_t resolution;    // 25ns * (resolution+1)
+    uint8_t checksum[4];   // of data after this point
+    uint8_t track[165][4]; // track offsets, not necessarily 165
+};
+
+enum
+{
+    SCP_FLAG_INDEXED    = (1<<0),
+    SCP_FLAG_96TPI      = (1<<1),
+    SCP_FLAG_360RPM     = (1<<2),
+    SCP_FLAG_NORMALIZED = (1<<3),
+    SCP_FLAG_READWRITE  = (1<<4),
+    SCP_FLAG_FOOTER     = (1<<5)
+};
+
+struct ScpTrack
+{
+    char track_id[3];      // 'TRK'
+    uint8_t strack;        // SCP track number
+    struct
+    {
+        uint8_t index[4];  // time for one revolution
+        uint8_t length[4]; // number of bitcells
+        uint8_t offset[4]; // offset to bitcell data, relative to track header
+    }
+    revolution[5];
+};
+
+#endif
--- a/tools/brother240tool.cc
+++ b/tools/brother240tool.cc
@@ -0,0 +1,56 @@
+#include "globals.h"
+#include "fmt/format.h"
+#include <fstream>
+
+static std::fstream inputFile;
+
+void syntax()
+{
+    std::cout << "Syntax: brother240tool <image>\n"
+                 "The disk image will be flipped from Brother to DOS format and back\n"
+                 "again.\n";
+    exit(0);
+}
+
+uint8_t getbyte(uint32_t offset)
+{
+    inputFile.seekg(offset, std::ifstream::beg);
+    return inputFile.get();
+}
+
+void putbyte(uint32_t offset, uint8_t value)
+{
+    inputFile.seekp(offset, std::ifstream::beg);
+    inputFile.put(value);
+}
+
+int main(int argc, const char* argv[])
+{
+    if (argc < 2)
+        syntax();
+    
+    inputFile.open(argv[1], std::ios::in | std::ios::out | std::ios::binary);
+    if (!inputFile.is_open())
+		Error() << fmt::format("cannot open input file '{}'", argv[1]);
+
+    uint8_t b1 = getbyte(0x015);
+    uint8_t b2 = getbyte(0x100);
+    if ((b1 == 0x58) && (b2 == 0x58))
+    {
+        std::cerr << "Flipping from Brother to DOS.\n";
+        putbyte(0x015, 0xf0);
+        putbyte(0x100, 0xf0);
+    }
+    else if ((b1 == 0xf0) && (b2 == 0xf0))
+    {
+        std::cerr << "Flipping from DOS to Brother.\n";
+        putbyte(0x015, 0x58);
+        putbyte(0x100, 0x58);
+    }
+    else
+        Error() << "Unknown image format.";
+
+    inputFile.close();
+    return 0;
+}
+
Author	SHA1	Message	Date
David Given	73419704c2	Merge pull request #118 from davidgiven/fixing Fix a few minor build tweaks.	2019-12-13 23:56:12 +01:00
David Given	a8b92d4780	This works; final tweaking.	2019-12-13 23:53:42 +01:00
David Given	98140b0646	More testing.	2019-12-13 23:50:33 +01:00
David Given	4429ce1f84	More build tweaks.	2019-12-13 23:48:17 +01:00
David Given	1f50941a2c	Merge from trunk.	2019-12-13 23:45:17 +01:00
David Given	a7de04848c	Merge pull request #117 from davidgiven/githubci Convert to Github CI instead of Travis.	2019-12-13 23:43:03 +01:00
David Given	c264fec6e9	The Windows stuff doesn't work, so let's shelve it for now.	2019-12-13 23:38:49 +01:00
David Given	4488b2542f	Update MSYS build environment.	2019-12-13 23:24:23 +01:00
David Given	2f1a5189d6	Oh, yeah, let's actually check out our project!	2019-12-13 23:21:58 +01:00
David Given	effaeff51e	Something's not right --- test.	2019-12-13 23:19:48 +01:00
David Given	1210549f59	Try Windows builds on github.	2019-12-13 23:12:29 +01:00
David Given	7200de9702	Add more Homebrew packages.	2019-12-13 23:02:13 +01:00
David Given	5dd5c8516a	Don't do builds on push_request, because these always coincide with pushes.	2019-12-13 23:01:08 +01:00
David Given	f7fb2a844b	Github's OSX doesn't install pkg-config by default?	2019-12-13 23:00:10 +01:00
David Given	20b1b2a4a8	More YAML syntax fiddling?	2019-12-13 22:58:28 +01:00
David Given	f8b8bc2295	Fiddle with YAML syntax.	2019-12-13 22:57:29 +01:00
David Given	2d4d56d09f	Try Github CI for OSX builds instead of Travis.	2019-12-13 22:55:37 +01:00
David Given	39599b76c8	Stop building the Ubuntu version with Travis.	2019-12-13 22:52:30 +01:00
David Given	c2c40ccfbb	Also remember to install ninja-build.	2019-12-13 22:48:48 +01:00
David Given	ab42eb23f4	Remember to run apt as sudo.	2019-12-13 22:47:20 +01:00
David Given	05eff0e528	Try to build using github CI.	2019-12-13 22:44:58 +01:00
David Given	23311b4b68	Start looking at Github CI.	2019-12-13 22:41:19 +01:00
David Given	5e97df8d15	Better diagnostics when a package can't be found.	2019-12-13 22:39:58 +01:00
David Given	898e8c551c	Produce a build-time error if the pkg-config packages aren't available.	2019-12-13 22:34:24 +01:00
David Given	ad69c6bd27	Fix stupid (but thankfully harmless) typo.	2019-12-13 22:33:39 +01:00
David Given	661399cc83	Update document with the new flippy mod doc; explain how Mac disks are broken.	2019-12-12 21:04:42 +01:00
David Given	edbb4b1daa	Merge pull request #115 from davidgiven/reading Rewrite the entire sampler.	2019-12-12 20:46:12 +01:00
David Given	6389e8a756	Update pin number (which was wrong).	2019-12-12 20:35:20 +01:00
David Given	c187b79d80	Add a 300RPM clock on 3[0] and a 360RPM clock on 3[1], for use with faking index pulses to the drive.	2019-12-12 20:34:44 +01:00
David Given	edbe624c5a	Hopefully, finally, fix the hang-on-read issue.	2019-12-12 20:09:49 +01:00
David Given	44e2334815	Typo fix. Make sure that both drives get deselected when the motor stops (to make the LEDs go out).	2019-12-12 00:17:59 +01:00
David Given	b448ab7917	Finally squeeze everything in to the Verilog sampler. It does seem to work better... the the USB hangup problem persists. Mac disks are still nigh-unreadable.	2019-12-12 00:12:20 +01:00
David Given	072a097003	Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've run into size limits for the device, and I need to slim down.	2019-12-11 22:51:27 +01:00
David Given	a66e704bab	Start ripping out the awful UDB-based sampler code, replacing it with a Verilog one and a standalone FIFO. This gets the FIFO working.	2019-12-11 21:13:57 +01:00
David Given	ed0d578b18	Merge pull request #114 from davidgiven/fixing1 Add support for measuring signal line voltages.	2019-12-11 00:28:13 +01:00
David Given	32bb956710	Detect voltage levels correctly.	2019-12-11 00:05:34 +01:00
David Given	f436d6b582	Add a feature where we can measure the FDD bus signal voltages using the PSoC's ADCs. Increase the track step pulse width to 6us, because.	2019-12-10 22:36:18 +01:00
David Given	8ee6eed4dc	Merge pull request #112 from davidgiven/fixing Rework the sequencer completely, because bizarrely writing disks just stopped working	2019-11-29 22:02:44 +01:00
David Given	3094c5c919	Add missing files.	2019-11-29 18:49:22 +01:00
David Given	1e012699af	Clean up the Verilog a bit.	2019-11-25 20:54:13 +01:00
David Given	91d6e9aeb9	Rewrite the sequencer engine with a separate fifo component and a pure verilog sequencer --- much easier to understand. We can write disks again!	2019-11-25 20:52:13 +01:00
David Given	a40b26ff46	Archival checkin for trying to figure out why writes no longer work.	2019-11-24 15:14:32 +01:00
David Given	ebcb9c4bb0	Switch the output lines to open-drain drive low.	2019-11-24 02:06:45 +01:00
David Given	2520834b18	Add the brother240tool program.	2019-11-24 01:46:02 +01:00
David Given	a1f3087046	Add an 8" drive datasheet.	2019-11-24 01:45:43 +01:00
David Given	e9670e205e	Don't erroneously crash out if the t and s parameters are omitted from the rpm command.	2019-10-14 22:25:43 +02:00
David Given	658e2b7295	Properly initialise flags. Fixes: #109	2019-09-22 21:55:37 +02:00
David Given	7b4a8d6de2	Merge pull request #108 from davidgiven/scp Add very beta support for scp import and export	2019-09-21 22:32:52 +02:00
David Given	e8f7b51aef	Another documentation tweak.	2019-09-21 22:15:44 +02:00
David Given	9d6bc57a5f	Update documentation.	2019-08-31 12:32:52 +02:00
David Given	73766f92b4	Fix the flux to scp converter.	2019-08-31 12:31:33 +02:00
David Given	80badf3b54	Remember to check in the build file changes...	2019-08-31 12:09:11 +02:00
David Given	116529f85a	Archival, non-working checkin of the flux to scp converter (it appears to produce garbage).	2019-08-31 01:41:11 +02:00
David Given	5a2b2bc07a	Allow support for command lines with non-argument filenames.	2019-08-31 01:40:44 +02:00