Merge pull request #118 from davidgiven/fixing

Fix a few minor build tweaks.
This works; final tweaking.
2025-10-24 11:11:02 -07:00 · 2019-12-13 23:56:12 +01:00 · 2019-12-13 23:53:42 +01:00 · 2019-12-13 23:50:33 +01:00 · 2019-12-13 23:48:17 +01:00 · 2019-12-13 23:45:17 +01:00
25 changed files with 1545 additions and 424 deletions
--- a/.github/workflows/ccpp.yml
+++ b/.github/workflows/ccpp.yml
@@ -0,0 +1,34 @@
+name: C/C++ CI
+
+on: [push]
+
+jobs:
+  build-linux:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: apt
+      run: sudo apt install libusb-1.0-0-dev libsqlite3-dev ninja-build
+    - name: make
+      run: make
+
+  build-macos:
+    runs-on: macos-latest
+    steps:
+    - uses: actions/checkout@v1
+    - name: brew
+      run: brew install sqlite pkg-config libusb ninja
+    - name: make
+      run: make
+
+#  build-windows:
+#    runs-on: windows-latest
+#    steps:
+#    - uses: numworks/setup-msys2@v1
+#      with:
+#        msystem: MSYS
+#    - uses: actions/checkout@v1
+#    - name: pacman
+#      run: msys2do pacman -S --noconfirm --needed make ninja mingw-w64-i686-libusb mingw-w64-i686-sqlite3 mingw-w64-i686-zlib mingw-w64-i686-gcc zip
+#    - name: make
+#      run: msys2do make
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,39 +0,0 @@
-language: shell
-git:
-    depth: 1
-
-matrix:
-    include:
-        -
-            os: linux
-            sudo: false
-            dist: xenial
-            compiler: gcc
-            env: CXX=g++-8
-            script:
-            - make
-        -
-            os: osx
-            osx_image: xcode10.2
-            compiler: clang
-            env:
-            - HOMEBREW_NO_INSTALL_CLEANUP=1
-
-addons:
-    apt:
-        sources:
-        - llvm-toolchain-precise-3.8
-        - ubuntu-toolchain-r-test
-        packages:
-        - ninja-build
-        - libusb-1.0-0-dev
-        - libsqlite3-dev
-        - g++-8
-    homebrew:
-        packages:
-        - ninja
-
-script:
- make
-
-
--- a/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
+++ b/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
@@ -1,244 +1,244 @@
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 :00000001FF
--- a/FluxEngine.cydsn/FIFOin/API/c.c
+++ b/FluxEngine.cydsn/FIFOin/API/c.c
@@ -0,0 +1,27 @@
+#include "cyfitter_cfg.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "`$INSTANCE_NAME`_h.h"
+
+void `$INSTANCE_NAME`_Start()
+{
+   `$INSTANCE_NAME`_Init();
+}    
+
+void `$INSTANCE_NAME`_Stop()
+{
+    `$INSTANCE_NAME`_Disable();
+}
+
+void `$INSTANCE_NAME`_Init()
+{    
+    `$INSTANCE_NAME`_Enable();
+    
+}
+void `$INSTANCE_NAME`_Enable()
+{
+}
+
+void `$INSTANCE_NAME`_Disable()
+{
+}
--- a/FluxEngine.cydsn/FIFOin/API/h.h
+++ b/FluxEngine.cydsn/FIFOin/API/h.h
@@ -0,0 +1,50 @@
+#if !defined(`$INSTANCE_NAME`_H)
+#define `$INSTANCE_NAME`_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" 
+
+#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
+
+    /* Macros to clear DP FIFOs.*/
+#define `$INSTANCE_NAME`_CLEAR do { \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
+    } while(0)
+
+/* Macros to set FIFO level mode. See the TRM for details */
+#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+#define `$INSTANCE_NAME`_SET_LEVEL_MID \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to set FIFO to single-buffer mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+
+/* Macros to return the FIFO to normal mode. */
+#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
+    CY_SET_XTND_REG8(\
+        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
+        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
+    
+void `$INSTANCE_NAME`_Enable();
+void `$INSTANCE_NAME`_Disable();
+void `$INSTANCE_NAME`_Start();
+void `$INSTANCE_NAME`_Stop();
+void `$INSTANCE_NAME`_Init();
+
+#endif
+
+/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOin/FIFOin.cysym
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.cysym
--- a/FluxEngine.cydsn/FIFOin/FIFOin.v
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.v
@@ -0,0 +1,128 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+
+/* Ultra-simple FIFO in component: a byte is shifted in every clock when req
+ * is high. */
+ 
+module FIFOin (drq, clk, d, req);
+	output  drq;
+	input   clk;
+	input  [7:0] d;
+	input  req;
+
+//`#start body` -- edit after this line, do not edit this line
+
+wire [7:0] pi;
+assign pi = d;
+
+wire load;
+assign load = req;
+
+cy_psoc3_dp #(.cy_dpconfig(
+{
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM0:    */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM1:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM2:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM3:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM4:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM5:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM6:     */
+	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+	`CS_CMP_SEL_CFGA, /*CFGRAM7:     */
+	8'hFF, 8'h00,	/*CFG9:     */
+	8'hFF, 8'hFF,	/*CFG11-10:     */
+	`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+	`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+	`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+	`SC_SI_A_DEFSI, /*CFG13-12:     */
+	`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
+	1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
+	`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+	`SC_FB_NOCHN, `SC_CMP1_NOCHN,
+	`SC_CMP0_NOCHN, /*CFG15-14:     */
+	10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+	`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
+	`SC_WRK16CAT_DSBL /*CFG17-16:     */
+}
+)) dp(
+	/* input          */ .clk(clk),
+	/* input [02:00]  */ .cs_addr(3'b0),    // Program counter
+	/* input          */ .route_si(1'b0),   // Shift in
+	/* input          */ .route_ci(1'b0),   // Carry in
+	/* input          */ .f0_load(load),    // Load FIFO 0
+	/* input          */ .f1_load(1'b0), 	// Load FIFO 1
+	/* input          */ .d0_load(1'b0), 	// Load Data Register 0
+	/* input          */ .d1_load(1'b0), 	// Load Data Register 1
+	/* output         */ .ce0(), 			// Accumulator 0 = Data register 0
+	/* output         */ .cl0(), 			// Accumulator 0 < Data register 0
+	/* output         */ .z0(), 			// Accumulator 0 = 0
+	/* output         */ .ff0(), 			// Accumulator 0 = FF
+	/* output         */ .ce1(), 			// Accumulator [0|1] = Data register 1
+	/* output         */ .cl1(), 			// Accumulator [0|1] < Data register 1
+	/* output         */ .z1(), 			// Accumulator 1 = 0
+	/* output         */ .ff1(), 			// Accumulator 1 = FF
+	/* output         */ .ov_msb(), 		// Operation over flow
+	/* output         */ .co_msb(), 		// Carry out
+	/* output         */ .cmsb(), 			// Carry out
+	/* output         */ .so(), 			// Shift out
+    /* output         */ .f0_bus_stat(drq), // not empty
+	/* output         */ .f0_blk_stat(full),// full
+	/* output         */ .f1_bus_stat(), 	// FIFO 1 status to uP
+	/* output         */ .f1_blk_stat(), 	// FIFO 1 status to DP
+	/* input          */ .ci(1'b0), 		// Carry in from previous stage
+	/* output         */ .co(), 			// Carry out to next stage
+	/* input          */ .sir(1'b0), 		// Shift in from right side
+	/* output         */ .sor(), 			// Shift out to right side
+	/* input          */ .sil(1'b0), 		// Shift in from left side
+	/* output         */ .sol(), 			// Shift out to left side
+	/* input          */ .msbi(1'b0), 		// MSB chain in
+	/* output         */ .msbo(), 			// MSB chain out
+	/* input [01:00]  */ .cei(2'b0),        // Compare equal in from prev stage
+	/* output [01:00] */ .ceo(),            // Compare equal out to next stage
+	/* input [01:00]  */ .cli(2'b0), 	    // Compare less than in from prv stage
+	/* output [01:00] */ .clo(),            // Compare less than out to next stage
+	/* input [01:00]  */ .zi(2'b0),         // Zero detect in from previous stage
+	/* output [01:00] */ .zo(),             // Zero detect out to next stage
+	/* input [01:00]  */ .fi(2'b0), 		// 0xFF detect in from previous stage
+	/* output [01:00] */ .fo(), 	        // 0xFF detect out to next stage
+	/* input [01:00]  */ .capi(2'b0),	    // Capture in from previous stage
+	/* output [01:00] */ .capo(),		    // Capture out to next stage
+	/* input          */ .cfbi(1'b0), 		// CRC Feedback in from previous stage
+	/* output         */ .cfbo(), 			// CRC Feedback out to next stage
+	/* input [07:00]  */ .pi(pi), 		    // Parallel data port
+	/* output [07:00] */ .po()              // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
--- a/FluxEngine.cydsn/FIFOout/API/c.c
+++ b/FluxEngine.cydsn/FIFOout/API/c.c
@@ -25,5 +25,3 @@ void `$INSTANCE_NAME`_Enable()
 void `$INSTANCE_NAME`_Disable()
 {
 }
-
-/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOout/FIFOout.v
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.v
@@ -20,8 +20,8 @@ module FIFOout (
 wire [7:0] po;
 assign d = po;

-localparam STATE_WAITFORREQ    = 1'b0;
-localparam STATE_READ          = 1'b1;
+localparam STATE_WAIT = 1'b0;
+localparam STATE_READ = 1'b1;

 reg state;
 reg oldreq;
@@ -31,7 +31,7 @@ assign ack = (state != STATE_READ);
 always @(posedge clk)
 begin
    case (state)
-        STATE_WAITFORREQ:
+        STATE_WAIT:
        begin
            if (!empty)
            begin
@@ -45,7 +45,7 @@ begin
        
        STATE_READ:
        begin
-            state <= STATE_WAITFORREQ;
+            state <= STATE_WAIT;
        end
    endcase
 end
--- a/FluxEngine.cydsn/FluxEngine.cydwr
+++ b/FluxEngine.cydsn/FluxEngine.cydwr
@@ -52,6 +52,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_8" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -171,6 +195,54 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="71bc291d-84a7-40a8-b7b2-1c8a34326a31">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="300" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK300" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK300" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="90ce0c72-9f10-44ef-a049-f0f525d59bea">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_FREQ" />
+        <Data key="desired_freq" value="128" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="65536" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="CLOCK8" />
+        <Data key="named_src_direct_connect" value="False" />
+        <Data key="netlist_name" value="CLOCK8" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
+        <Data key="src_clk_name" value="IMO" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="349ffa20-8576-4ac3-9a6f-34ef606de6cf">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -194,6 +266,29 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="OUTPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\OUTPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="6616e828-6611-4893-a674-66c861d79d6c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -265,6 +360,53 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="09974428-e912-491f-8d2f-361ba50e7599">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_6" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_6" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
+      <Group key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a">
+        <Data key="check_tolerance" value="False" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="AUTO" />
+        <Data key="desired_freq" value="1600000" />
+        <Data key="desired_unit" value="0" />
+        <Data key="divider" value="40" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="INPUT_VOLTAGE_ADC_theACLK" />
+        <Data key="netlist_name" value="\INPUT_VOLTAGE_ADC:theACLK\" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
+        <Data key="src_clk_name" value="MASTER_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="b762c287-7f87-4b21-982e-84be01dc5115">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -312,6 +454,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="b722443b-8f81-46dc-bf9b-c95eb62bc181">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_1" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_1" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -336,6 +502,30 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
+      <Group key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f">
+        <Data key="check_tolerance" value="True" />
+        <Data key="clock_version" value="v1" />
+        <Data key="derive_type" value="NAMED_DIVIDER" />
+        <Data key="desired_freq" value="0" />
+        <Data key="desired_unit" value="15" />
+        <Data key="divider" value="0" />
+        <Data key="domain" value="DIGITAL" />
+        <Data key="enabled" value="True" />
+        <Data key="minus_accuracy" value="0.25" />
+        <Data key="minus_tolerance" value="5" />
+        <Data key="name" value="Clock_7" />
+        <Data key="named_src_direct_connect" value="True" />
+        <Data key="netlist_name" value="Clock_7" />
+        <Data key="placement" value="AUTO" />
+        <Data key="plus_accuracy" value="0.25" />
+        <Data key="plus_tolerance" value="5" />
+        <Data key="scope" value="LOCAL" />
+        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
+        <Data key="src_clk_name" value="BUS_CLK" />
+        <Data key="start_on_reset" value="True" />
+        <Data key="sync_with_bus_clk" value="True" />
+        <Data key="user_set_domain" value="False" />
+      </Group>
      <Group key="e4a53a4c-40e1-4747-a72a-10193ffdf31c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -634,18 +824,26 @@
    <Group key="Clock">
      <Data key="0b2f9bbb-00ce-4115-a788-ffb9d046a9e5" value="Clock_4" />
      <Data key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b" value="Clock_5" />
+      <Data key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2" value="Clock_8" />
      <Data key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4" value="Clock_3" />
      <Data key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec" value="CounterClock" />
      <Data key="24cd38f7-f472-4403-837f-86807c8f5333" value="PULSE_CLOCK" />
      <Data key="63ed4137-0b09-4256-8a27-35c9a2653f1a" value="Clock_2" />
      <Data key="66f14071-bddd-4b4d-a9aa-a129cceaa7b6" value="Clock_3" />
+      <Data key="71bc291d-84a7-40a8-b7b2-1c8a34326a31" value="CLOCK300" />
+      <Data key="90ce0c72-9f10-44ef-a049-f0f525d59bea" value="CLOCK8" />
      <Data key="349ffa20-8576-4ac3-9a6f-34ef606de6cf" value="Clock_1" />
+      <Data key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a" value="OUTPUT_VOLTAGE_ADC_theACLK" />
      <Data key="6616e828-6611-4893-a674-66c861d79d6c" value="SignalSamplingClock" />
      <Data key="12664fc6-9d70-44b1-8a49-887a292e1b7f" value="Clock_3" />
      <Data key="75187c05-9501-4450-b306-6ccdd3bb77db" value="Clock_5" />
+      <Data key="09974428-e912-491f-8d2f-361ba50e7599" value="Clock_6" />
+      <Data key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a" value="INPUT_VOLTAGE_ADC_theACLK" />
      <Data key="b762c287-7f87-4b21-982e-84be01dc5115" value="Clock_2" />
      <Data key="b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358" value="UART_IntClock" />
+      <Data key="b722443b-8f81-46dc-bf9b-c95eb62bc181" value="Clock_1" />
      <Data key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c" value="CounterClock" />
+      <Data key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f" value="Clock_7" />
      <Data key="e4a53a4c-40e1-4747-a72a-10193ffdf31c" value="Clock_1" />
      <Data key="efd5f185-0c32-4824-ba72-3ceb5356f5a7" value="Clock_1" />
    </Group>
@@ -670,10 +868,11 @@
      <Data key="c5367cde-21d5-4866-9a32-d16abfea0c61" value="WPT" />
      <Data key="d19368c5-6855-41bb-a9ff-808938abef00" value="INDEX" />
      <Data key="e9f14b5a-b2bf-49b8-98f3-d7b5a43ace8d" value="DRVSB" />
-      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED_PIN" />
+      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="INDEX300" />
      <Data key="e51063a9-4fad-40c7-a06b-7cc4b137dc18" value="DSKCHG" />
      <Data key="ea7ee228-8b3f-426c-8bb8-cd7a81937769" value="DIR" />
      <Data key="ed092b9b-d398-4703-be89-cebf998501f6" value="UartTx" />
+      <Data key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663" value="INDEX360" />
      <Data key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="UART_tx" />
      <Data key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b" value="DRVSA" />
      <Data key="fff78075-035e-43d7-8577-bc5be4d21926" value="WGATE" />
@@ -3946,7 +4145,7 @@
    </Group>
    <Group key="e851a3b9-efb8-48be-bbb8-b303b216c393">
      <Group key="0">
-        <Data key="Port Format" value="2,1" />
+        <Data key="Port Format" value="3,0" />
      </Group>
    </Group>
    <Group key="e51063a9-4fad-40c7-a06b-7cc4b137dc18">
@@ -3964,6 +4163,11 @@
        <Data key="Port Format" value="12,7" />
      </Group>
    </Group>
+    <Group key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663">
+      <Group key="0">
+        <Data key="Port Format" value="3,1" />
+      </Group>
+    </Group>
    <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
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        <Data key="Port Format" value="12,7" />
--- a/FluxEngine.cydsn/FluxEngine.cyprj
+++ b/FluxEngine.cydsn/FluxEngine.cyprj
@@ -1127,20 +1127,20 @@
 <CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
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-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
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 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="CAPTURE_DMA_dma.c" persistent="Generated_Source\PSoC5\CAPTURE_DMA_dma.c">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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 <PropertyDeltas />
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 <CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="CAPTURE_DMA_dma.h" persistent="Generated_Source\PSoC5\CAPTURE_DMA_dma.h">
-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
 <build_action v="HEADER;;;;" />
 <PropertyDeltas />
@@ -1153,20 +1153,20 @@
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-<Hidden v="False" />
+<Hidden v="True" />
 </CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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-<Hidden v="False" />
+<Hidden v="True" />
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-<Hidden v="False" />
+<Hidden v="True" />
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@@ -1382,13 +1382,13 @@
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-<Hidden v="False" />
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+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
+<dependencies>
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+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="OTHER;;;;" />
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+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
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+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="SuperCounter.v" persistent="SuperCounter\SuperCounter.v">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="OTHER;;;;" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>
+</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2872,6 +3281,6 @@
 </ignored_deps>
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
 <boot_component v="" />
-<current_generation v="69" />
+<current_generation v="84" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
--- a/FluxEngine.cydsn/Sampler/Sampler.v
+++ b/FluxEngine.cydsn/Sampler/Sampler.v
@@ -0,0 +1,134 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+`include "../SuperCounter/SuperCounter.v"
+
+//`#end` -- edit above this line, do not edit this line
+// Generated on 12/11/2019 at 21:18
+// Component: Sampler
+module Sampler (
+	output [2:0] debug_state,
+	output reg [7:0] opcode,
+	output  req,
+	input   clock,
+	input   index,
+	input   rdata,
+	input   reset,
+	input   sampleclock
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+localparam STATE_RESET = 0;
+localparam STATE_WAITING = 1;
+localparam STATE_INTERVAL = 2;
+localparam STATE_DISPATCH = 3;
+localparam STATE_OPCODE = 4;
+localparam STATE_COUNTING = 5;
+
+reg [2:0] state;
+wire [6:0] counter;
+
+wire countnow;
+assign countnow = (state == STATE_COUNTING);
+
+wire counterreset;
+assign counterreset = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+SuperCounter #(.Delta(1), .ResetValue(0)) Counter
+(
+    /* input */ .clk(clock),
+    /* input */ .reset(counterreset),
+    /* input */ .count(countnow),
+    /* output */ .d(counter)
+);
+
+reg oldsampleclock;
+wire sampleclocked;
+assign sampleclocked = !oldsampleclock && sampleclock;
+
+reg oldindex;
+wire indexed;
+assign indexed = !oldindex && index;
+
+wire rdataed;
+reg oldrdata;
+assign rdataed = !oldrdata && rdata;
+
+assign req = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
+
+always @(posedge clock)
+begin
+    if (reset)
+    begin
+        state <= STATE_RESET;
+        opcode <= 0;
+        oldsampleclock <= 0;
+        oldindex <= 0;
+        oldrdata <= 0;
+    end
+    else
+        case (state)
+            STATE_RESET:
+                state <= STATE_WAITING;
+            
+            STATE_WAITING:
+            begin
+                if (rdataed || indexed)
+                begin
+                    opcode <= {0, counter};
+                    state <= STATE_INTERVAL;
+                end
+                else if (sampleclocked)
+                begin
+                    oldsampleclock <= 1;
+                    if (counter == 7'h7f)
+                    begin
+                        opcode <= {0, counter};
+                        state <= STATE_OPCODE;
+                    end
+                    else
+                        state <= STATE_COUNTING;
+                end
+                
+                if (oldrdata && !rdata)
+                    oldrdata <= 0;
+                if (oldindex && !index)
+                    oldindex <= 0;
+                if (oldsampleclock && !sampleclock)
+                    oldsampleclock <= 0;
+            end
+            
+            STATE_INTERVAL: /* interval byte sent here; counter reset */
+                state <= STATE_DISPATCH;
+                
+            STATE_DISPATCH: /* relax after interval byte, dispatch for opcode */
+            begin
+                if (rdataed)
+                begin
+                    oldrdata <= 1;
+                    opcode <= 8'h80;
+                    state <= STATE_OPCODE;
+                end
+                else if (indexed)
+                begin
+                    oldindex <= 1;
+                    opcode <= 8'h81;
+                    state <= STATE_OPCODE;
+                end
+                else
+                    state <= STATE_WAITING;
+            end
+            
+            STATE_OPCODE: /* opcode byte sent here */
+                state <= STATE_WAITING;
+                            
+            STATE_COUNTING:
+                state <= STATE_WAITING;
+        endcase
+end
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/Sequencer/Sequencer.v
+++ b/FluxEngine.cydsn/Sequencer/Sequencer.v
@@ -92,6 +92,8 @@ begin
            STATE_INDEXING:
                if (indexed)
                    state <= STATE_LOAD;
+                else
+                    state <= STATE_INDEXING;
        endcase
 end

--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.v
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.v
@@ -0,0 +1,156 @@
+
+//`#start header` -- edit after this line, do not edit this line
+`include "cypress.v"
+//`#end` -- edit above this line, do not edit this line
+// Generated on 11/16/2017 at 15:44
+// Component: FIFOout
+module SuperCounter (
+	input clk,
+    input reset,
+    input count,
+    output [7:0] d,
+	output drq,
+	output empty,
+    output ack
+);
+
+//`#start body` -- edit after this line, do not edit this line
+
+parameter ResetValue = 0;
+parameter Delta = 1;
+    
+wire [7:0] po;
+assign d = po;
+
+localparam STATE_RESET = 0;
+localparam STATE_WAIT = 1;
+localparam STATE_ADD = 2;
+
+reg oldcount;
+wire counted;
+assign counted = count && !oldcount;
+
+always @(posedge clk) oldcount <= count;
+
+wire [2:0] cs;
+assign cs = reset ? STATE_RESET : (counted ? STATE_ADD : STATE_WAIT);
+            
+cy_psoc3_dp #(.d0_init(ResetValue), .d1_init(Delta), 
+.cy_dpconfig(
+{
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM0:  STATE_RESET*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM1:  STATE_WAIT*/
+    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D1,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM2:  STATE_ADD*/
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM3:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM4:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM5:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM6:             */
+    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
+    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
+    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
+    `CS_CMP_SEL_CFGA, /*CFGRAM7:             */
+    8'hFF, 8'h00,  /*CFG9:             */
+    8'hFF, 8'hFF,  /*CFG11-10:             */
+    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
+    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
+    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
+    `SC_SI_A_DEFSI, /*CFG13-12:             */
+    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
+    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
+    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
+    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
+    `SC_CMP0_NOCHN, /*CFG15-14:             */
+    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
+    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
+    `SC_WRK16CAT_DSBL /*CFG17-16:             */
+}
+)) dp(
+        /*  input                   */  .reset(1'b0),
+        /*  input                   */  .clk(clk),
+        /*  input   [02:00]         */  .cs_addr(cs),
+        /*  input                   */  .route_si(1'b0),
+        /*  input                   */  .route_ci(1'b0),
+        /*  input                   */  .f0_load(1'b0),
+        /*  input                   */  .f1_load(1'b0),
+        /*  input                   */  .d0_load(1'b0),
+        /*  input                   */  .d1_load(1'b0),
+        /*  output                  */  .ce0(),
+        /*  output                  */  .cl0(),
+        /*  output                  */  .z0(),
+        /*  output                  */  .ff0(),
+        /*  output                  */  .ce1(),
+        /*  output                  */  .cl1(),
+        /*  output                  */  .z1(),
+        /*  output                  */  .ff1(),
+        /*  output                  */  .ov_msb(),
+        /*  output                  */  .co_msb(),
+        /*  output                  */  .cmsb(),
+        /*  output                  */  .so(),
+        /*  output                  */  .f0_bus_stat(),
+        /*  output                  */  .f0_blk_stat(),
+        /*  output                  */  .f1_bus_stat(),
+        /*  output                  */  .f1_blk_stat(),
+        
+        /* input                    */  .ci(1'b0),     // Carry in from previous stage
+        /* output                   */  .co(),// Carry out to next stage
+        /* input                    */  .sir(1'b0),    // Shift in from right side
+        /* output                   */  .sor(),        // Shift out to right side
+        /* input                    */  .sil(1'b0),    // Shift in from left side
+        /* output                   */  .sol(),        // Shift out to left side
+        /* input                    */  .msbi(1'b0),   // MSB chain in
+        /* output                   */  .msbo(),       // MSB chain out
+        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
+        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
+        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
+        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
+        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
+        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
+        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
+        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
+        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
+        /* output [01:00]           */  .capo(),       // Software capture to next stage
+        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
+        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
+        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
+        /* output [07:00]           */  .po(po)       // Parallel data port
+);
+
+//`#end` -- edit above this line, do not edit this line
+endmodule
+//`#start footer` -- edit after this line, do not edit this line
+//`#end` -- edit above this line, do not edit this line
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- a/FluxEngine.cydsn/TopDesign/TopDesign.cysch
+++ b/FluxEngine.cydsn/TopDesign/TopDesign.cysch
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
--- a/FluxEngine.cydsn/main.c
+++ b/FluxEngine.cydsn/main.c
@@ -85,10 +85,21 @@ static void print(const char* msg, ...)
    UART_PutCRLF();
 }

+static void set_drive_flags(uint8_t flags)
+{
+    if (current_drive_flags != flags)
+        homed = false;
+    
+    current_drive_flags = flags;
+    DRIVESELECT_REG_Write((flags & 1) ? 2 : 1); /* select drive 1 or 0 */
+    DENSITY_REG_Write(flags >> 1); /* density bit */
+}
+
 static void start_motor(void)
 {
    if (!motor_on)
    {
+        set_drive_flags(current_drive_flags);
        MOTOR_REG_Write(1);
        CyDelay(1000);
        homed = false;
@@ -104,6 +115,7 @@ static void stop_motor(void)
    if (motor_on)
    {
        MOTOR_REG_Write(0);
+        DRIVESELECT_REG_Write(0); /* deselect all drives */
        motor_on = false;
    }
 }
@@ -265,7 +277,7 @@ static void deinit_dma(void)

 static void init_capture_dma(void)
 {
-    dma_channel = CAPTURE_DMA_DmaInitialize(
+    dma_channel = SAMPLER_DMA_DmaInitialize(
        2 /* bytes */,
        true /* request per burst */, 
        HI16(CYDEV_PERIPH_BASE),
@@ -280,8 +292,8 @@ static void init_capture_dma(void)
            nexti = 0;

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],   
-            CY_DMA_TD_INC_DST_ADR | CAPTURE_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&SAMPLER_DATAPATH_F0_REG), LO16((uint32)&dma_buffer[i]));
+            CY_DMA_TD_INC_DST_ADR | SAMPLER_DMA__TD_TERMOUT_EN);
+        CyDmaTdSetAddress(td[i], LO16((uint32)SAMPLER_FIFO_FIFO_PTR), LO16((uint32)&dma_buffer[i]));
    }    
 }

@@ -292,13 +304,11 @@ static void cmd_read(struct read_frame* f)
    
    /* Do slow setup *before* we go into the real-time bit. */
    
-    SAMPLER_CONTROL_Write(1); /* reset */
-    
    {
        uint8_t i = CyEnterCriticalSection();
-        SAMPLER_DATAPATH_F0_SET_LEVEL_MID;
-        SAMPLER_DATAPATH_F0_CLEAR;
-        SAMPLER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
+        SAMPLER_FIFO_SET_LEVEL_MID;
+        SAMPLER_FIFO_CLEAR;
+        SAMPLER_FIFO_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    
@@ -320,7 +330,6 @@ static void cmd_read(struct read_frame* f)
    dma_reading_from_td = -1;
    dma_underrun = false;
    int count = 0;
-    SAMPLER_CONTROL_Write(0); /* !reset */
    CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
    CyDmaClearPendingDrq(dma_channel);
    CyDmaChEnable(dma_channel, 1);
@@ -386,12 +395,14 @@ abort:;

    donecrunch(&cs);
    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
-    unsigned zz = cs.outputlen;
-    if (cs.outputlen != BUFFER_SIZE)
-        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+    if (!dma_underrun)
+    {
+        if (cs.outputlen != BUFFER_SIZE)
+            USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
+        wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
+    }
    if ((cs.outputlen == BUFFER_SIZE) || (cs.outputlen == 0))
        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, NULL, 0);
-    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
    deinit_dma();

    if (dma_underrun)
@@ -404,7 +415,7 @@ abort:;
        DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_READ_REPLY);
        send_reply(&r);
    }
-    print("count=%d i=%d d=%d zz=%d", count, index_irq, dma_underrun, zz);
+    print("count=%d i=%d d=%d", count, index_irq, dma_underrun);
 }

 static void init_replay_dma(void)
@@ -622,16 +633,6 @@ static void cmd_erase(struct erase_frame* f)
    send_reply((struct any_frame*) &r);
 }

-static void set_drive_flags(uint8_t flags)
-{
-    if (current_drive_flags != flags)
-        homed = false;
-    
-    current_drive_flags = flags;
-    DRIVESELECT_REG_Write((flags & 1) ? 2 : 1); /* select drive 1 or 0 */
-    DENSITY_REG_Write(flags >> 1); /* density bit */
-}
-
 static void cmd_set_drive(struct set_drive_frame* f)
 {
    set_drive_flags(f->drive_flags);
@@ -789,7 +790,7 @@ int main(void)
    CySysTickStart();
    CySysTickSetCallback(4, system_timer_cb);
    INDEX_IRQ_StartEx(&index_irq_cb);
-    CAPTURE_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
+    SAMPLER_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
    SEQUENCER_DMA_FINISHED_IRQ_StartEx(&replay_dma_finished_irq_cb);
    INPUT_VOLTAGE_ADC_Stop();
    OUTPUT_VOLTAGE_ADC_Stop();
@@ -809,10 +810,7 @@ int main(void)
        {
            uint32_t time_on = clock - motor_on_time;
            if (time_on > MOTOR_ON_TIME)
-            {
-                MOTOR_REG_Write(0);
-                motor_on = false;
-            }
+                stop_motor();
        }
        
        if (!USBFS_GetConfiguration() || USBFS_IsConfigurationChanged())
--- a/7
+++ b/7
@@ -13,6 +13,13 @@ export LDFLAGS +=
 export LIBS = -static -lz -lsqlite3 -lusb-1.0
 export EXTENSION = .exe
 else
+
+packages-exist = $(shell pkg-config --exists $(PACKAGES) && echo yes)
+ifneq ($(packages-exist),yes)
+$(warning These pkg-config packages are installed: $(shell pkg-config --list-all | sort | awk '{print $$1}'))
+$(error You must have these pkg-config packages installed: $(PACKAGES))
+endif
+
 export CXX = g++
 export AR = ar rcs
 export STRIP = strip
--- a/README.md
+++ b/README.md
@@ -89,7 +89,7 @@ people who've had it work).
 | [Brother 120kB](doc/disk-brother.md)     |  🦄   |        |                                     |
 | [Brother 240kB](doc/disk-brother.md)     |  🦄   |   🦄   |                                     |
 | [Brother FB-100](doc/disk-fb100.md)      |  🦖   |        | Tandy Model 100, Husky Hunter, knitting machines |
-| [Macintosh 800kB](doc/disk-macintosh.md) |  🦄   |        | and probably the 400kB too          |
+| [Macintosh 800kB](doc/disk-macintosh.md) |  🦖   |        | and probably the 400kB too          |
 | [TRS-80](doc/disk-trs80.md)              |  🦖   |        | a minor variation of the IBM scheme |
 {: .datatable }

--- a/doc/Index_sensor_mod_FDD_1.1.pdf
+++ b/doc/Index_sensor_mod_FDD_1.1.pdf
--- a/doc/disk-macintosh.md
+++ b/doc/disk-macintosh.md
@@ -28,8 +28,16 @@ for example the Commodore 64 1541 drive, changed bitrate this way.
 But Macintosh disks used a constant bitrate and changed the speed that the
 disk spun instead to achieve the same effect...

-_Anyway_: FluxEngine will read them fine on a conventional drive. Because
-it's clever.
+_Anyway_: FluxEngine will read them fine on conventional drives.
+Because it's clever.
+
+**Big note.** Apparently --- and I'm still getting to the bottom of this ---
+some drives work and some don't. My drives produce about 90% good reads of
+known good disks. One rumour I've heard is that drives sometimes include
+filters which damage the signals at very particular intervals which Mac disks
+use, but frankly this seems unlikely; it could be a software issue at my end
+and I'm investigating. If you have any insight, please [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).

 Reading discs
 -------------
--- a/doc/faq.md
+++ b/doc/faq.md
@@ -48,7 +48,7 @@ haven't had the chance to try it end-for-end. I really need a hard-sectored

 **Q.** Does it work with flippy disks?

-Uhhh... probably not.
+Uhhh... maybe?

 So the problem with flippy disks (5.25" single-sided disks which could be
 inserted upside down to read the second side) is the index hole. Trouble is,
@@ -79,16 +79,21 @@ the other. But a flippy disk has both sets of tracks in the same place,
 because they're both accessed using the side 0 head...

 The only real way round this is to modify a 5.25" drive. That's _seriously_
-not in FluxEngine's remit. Sorry.
+not in FluxEngine's remit, but I've had some [excellent documentation
+contributed](Index_sensor_mod_FDD_1.1.pdf) on how to do this. I've never done
+it myself; if you try this and it works/doesn't work, as always, [get in
+touch](https://github.com/davidgiven/fluxengine/issues/new).

-**Q.** Is this like KryoFlux / Catweasel / DiskFerret? Do you support KryoFlux
+**Q.** Is this like Supercard Pro / KryoFlux / Catweasel / DiskFerret? Do you
+*support KryoFlux
 stream files?

 **A.** It's very like all of these; the idea's old, and lots of people have
 tried it (you can get away with any sufficiently fast microcontroller and
 enough RAM). FluxEngine can read from KryoFlux stream files natively, and
-there's a tool which will let you convert at least one kind of Catweasel file
-to FluxEngine's native flux file format.
+there's a tool which will let you convert at least one kind of Catweasel
+files and Supercard Pro files to and from FluxEngine's native flux file
+format.

 **Q.** Can I use this to make exact copies of disks?

--- a/src/fe-fluxtoscp.cc
+++ b/src/fe-fluxtoscp.cc
@@ -85,7 +85,7 @@ int mainConvertFluxToScp(int argc, const char* argv[])
    fileheader.file_id[0] = 'S';
    fileheader.file_id[1] = 'C';
    fileheader.file_id[2] = 'P';
-    fileheader.file_id[3] = 0x18; /* Version 1.8 of the spec */
+    fileheader.version = 0x18; /* Version 1.8 of the spec */
    fileheader.type = diskType;
    fileheader.revolutions = 5;
    fileheader.start_track = 0;
Author	SHA1	Message	Date
David Given	73419704c2	Merge pull request #118 from davidgiven/fixing Fix a few minor build tweaks.	2019-12-13 23:56:12 +01:00
David Given	a8b92d4780	This works; final tweaking.	2019-12-13 23:53:42 +01:00
David Given	98140b0646	More testing.	2019-12-13 23:50:33 +01:00
David Given	4429ce1f84	More build tweaks.	2019-12-13 23:48:17 +01:00
David Given	1f50941a2c	Merge from trunk.	2019-12-13 23:45:17 +01:00
David Given	a7de04848c	Merge pull request #117 from davidgiven/githubci Convert to Github CI instead of Travis.	2019-12-13 23:43:03 +01:00
David Given	c264fec6e9	The Windows stuff doesn't work, so let's shelve it for now.	2019-12-13 23:38:49 +01:00
David Given	4488b2542f	Update MSYS build environment.	2019-12-13 23:24:23 +01:00
David Given	2f1a5189d6	Oh, yeah, let's actually check out our project!	2019-12-13 23:21:58 +01:00
David Given	effaeff51e	Something's not right --- test.	2019-12-13 23:19:48 +01:00
David Given	1210549f59	Try Windows builds on github.	2019-12-13 23:12:29 +01:00
David Given	7200de9702	Add more Homebrew packages.	2019-12-13 23:02:13 +01:00
David Given	5dd5c8516a	Don't do builds on push_request, because these always coincide with pushes.	2019-12-13 23:01:08 +01:00
David Given	f7fb2a844b	Github's OSX doesn't install pkg-config by default?	2019-12-13 23:00:10 +01:00
David Given	20b1b2a4a8	More YAML syntax fiddling?	2019-12-13 22:58:28 +01:00
David Given	f8b8bc2295	Fiddle with YAML syntax.	2019-12-13 22:57:29 +01:00
David Given	2d4d56d09f	Try Github CI for OSX builds instead of Travis.	2019-12-13 22:55:37 +01:00
David Given	39599b76c8	Stop building the Ubuntu version with Travis.	2019-12-13 22:52:30 +01:00
David Given	c2c40ccfbb	Also remember to install ninja-build.	2019-12-13 22:48:48 +01:00
David Given	ab42eb23f4	Remember to run apt as sudo.	2019-12-13 22:47:20 +01:00
David Given	05eff0e528	Try to build using github CI.	2019-12-13 22:44:58 +01:00
David Given	23311b4b68	Start looking at Github CI.	2019-12-13 22:41:19 +01:00
David Given	5e97df8d15	Better diagnostics when a package can't be found.	2019-12-13 22:39:58 +01:00
David Given	898e8c551c	Produce a build-time error if the pkg-config packages aren't available.	2019-12-13 22:34:24 +01:00
David Given	ad69c6bd27	Fix stupid (but thankfully harmless) typo.	2019-12-13 22:33:39 +01:00
David Given	661399cc83	Update document with the new flippy mod doc; explain how Mac disks are broken.	2019-12-12 21:04:42 +01:00
David Given	edbb4b1daa	Merge pull request #115 from davidgiven/reading Rewrite the entire sampler.	2019-12-12 20:46:12 +01:00
David Given	6389e8a756	Update pin number (which was wrong).	2019-12-12 20:35:20 +01:00
David Given	c187b79d80	Add a 300RPM clock on 3[0] and a 360RPM clock on 3[1], for use with faking index pulses to the drive.	2019-12-12 20:34:44 +01:00
David Given	edbe624c5a	Hopefully, finally, fix the hang-on-read issue.	2019-12-12 20:09:49 +01:00
David Given	44e2334815	Typo fix. Make sure that both drives get deselected when the motor stops (to make the LEDs go out).	2019-12-12 00:17:59 +01:00
David Given	b448ab7917	Finally squeeze everything in to the Verilog sampler. It does seem to work better... the the USB hangup problem persists. Mac disks are still nigh-unreadable.	2019-12-12 00:12:20 +01:00
David Given	072a097003	Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've run into size limits for the device, and I need to slim down.	2019-12-11 22:51:27 +01:00
David Given	a66e704bab	Start ripping out the awful UDB-based sampler code, replacing it with a Verilog one and a standalone FIFO. This gets the FIFO working.	2019-12-11 21:13:57 +01:00