Merge from master.

Skeleton, non-functional microbee front end.
2025-10-24 11:11:02 -07:00 · 2019-10-14 22:27:26 +02:00 · 2019-08-26 23:15:45 +02:00
66 changed files with 2469 additions and 3960 deletions
--- a/.appveyor.yml
+++ b/.appveyor.yml
@@ -15,7 +15,7 @@ install:

 build_script:
  - make
-  - zip -9 fluxengine.zip fluxengine.exe brother120tool.exe brother240tool.exe FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
+  - zip -9 fluxengine.zip fluxengine.exe brother120tool.exe FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex

 artifacts:
  - path: fluxengine.zip
--- a/.github/workflows/ccpp.yml
+++ b/.github/workflows/ccpp.yml
@@ -1,41 +0,0 @@
-name: C/C++ CI
-
-on: [push]
-
-jobs:
-  build-linux:
-    runs-on: ubuntu-latest
-    steps:
-    - uses: actions/checkout@v1
-      with:
-        fetch-depth: 1
-    - name: apt
-      run: sudo apt install libusb-1.0-0-dev libsqlite3-dev ninja-build
-    - name: make
-      run: make
-
-  build-macos:
-    runs-on: macos-latest
-    steps:
-    - uses: actions/checkout@v1
-      with:
-        fetch-depth: 1
-    - name: brew
-      run: brew install sqlite pkg-config libusb ninja
-    - name: make
-      run: make
-
-#  build-windows:
-#    runs-on: windows-latest
-#    steps:
-#    - uses: numworks/setup-msys2@v1
-#      with:
-#        path-type: inherit
-#    - uses: actions/checkout@v1
-#    - name: pacman
-#      run: |
-#        msys2do pacman -S --noconfirm --needed make ninja mingw-w64-i686-libusb mingw-w64-i686-sqlite3 mingw-w64-i686-zlib mingw-w64-i686-gcc zip
-#    - name: build
-#      run: |
-#        msys2do make
-
--- a/.travis.yml
+++ b/.travis.yml
@@ -0,0 +1,39 @@
+language: shell
+git:
+    depth: 1
+
+matrix:
+    include:
+        -
+            os: linux
+            sudo: false
+            dist: xenial
+            compiler: gcc
+            env: CXX=g++-8
+            script:
+            - make
+        -
+            os: osx
+            osx_image: xcode10.2
+            compiler: clang
+            env:
+            - HOMEBREW_NO_INSTALL_CLEANUP=1
+
+addons:
+    apt:
+        sources:
+        - llvm-toolchain-precise-3.8
+        - ubuntu-toolchain-r-test
+        packages:
+        - ninja-build
+        - libusb-1.0-0-dev
+        - libsqlite3-dev
+        - g++-8
+    homebrew:
+        packages:
+        - ninja
+
+script:
+- make
+
+
--- a/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
+++ b/FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex
@@ -1,234 +1,234 @@
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@@ -4615,12 +4615,12 @@
 :0200000490105A
 :04000000BC90ACAF55
 :0200000490303A
-:0200000001A954
+:020000004C1A98
 :0200000490402A
 :4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0
 :400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080
 :400080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040
 :4000C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 :0200000490501A
-:0C00000000012E16106900002E301212B4
+:0C00000000012E16106900002E2A5C83FF
 :00000001FF
--- a/FluxEngine.cydsn/FIFOin/API/c.c
+++ b/FluxEngine.cydsn/FIFOin/API/c.c
@@ -1,27 +0,0 @@
-#include "cyfitter_cfg.h"
-#include "cydevice_trm.h"
-#include "cyfitter.h"
-#include "`$INSTANCE_NAME`_h.h"
-
-void `$INSTANCE_NAME`_Start()
-{
-   `$INSTANCE_NAME`_Init();
-}    
-
-void `$INSTANCE_NAME`_Stop()
-{
-    `$INSTANCE_NAME`_Disable();
-}
-
-void `$INSTANCE_NAME`_Init()
-{    
-    `$INSTANCE_NAME`_Enable();
-    
-}
-void `$INSTANCE_NAME`_Enable()
-{
-}
-
-void `$INSTANCE_NAME`_Disable()
-{
-}
--- a/FluxEngine.cydsn/FIFOin/API/h.h
+++ b/FluxEngine.cydsn/FIFOin/API/h.h
@@ -1,50 +0,0 @@
-#if !defined(`$INSTANCE_NAME`_H)
-#define `$INSTANCE_NAME`_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h" 
-
-#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
-
-    /* Macros to clear DP FIFOs.*/
-#define `$INSTANCE_NAME`_CLEAR do { \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
-    } while(0)
-
-/* Macros to set FIFO level mode. See the TRM for details */
-#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-#define `$INSTANCE_NAME`_SET_LEVEL_MID \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-
-/* Macros to set FIFO to single-buffer mode. */
-#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-
-/* Macros to return the FIFO to normal mode. */
-#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-    
-void `$INSTANCE_NAME`_Enable();
-void `$INSTANCE_NAME`_Disable();
-void `$INSTANCE_NAME`_Start();
-void `$INSTANCE_NAME`_Stop();
-void `$INSTANCE_NAME`_Init();
-
-#endif
-
-/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOin/FIFOin.cysym
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.cysym
--- a/FluxEngine.cydsn/FIFOin/FIFOin.v
+++ b/FluxEngine.cydsn/FIFOin/FIFOin.v
@@ -1,128 +0,0 @@
-
-//`#start header` -- edit after this line, do not edit this line
-`include "cypress.v"
-//`#end` -- edit above this line, do not edit this line
-
-/* Ultra-simple FIFO in component: a byte is shifted in every clock when req
- * is high. */
- 
-module FIFOin (drq, clk, d, req);
-	output  drq;
-	input   clk;
-	input  [7:0] d;
-	input  req;
-
-//`#start body` -- edit after this line, do not edit this line
-
-wire [7:0] pi;
-assign pi = d;
-
-wire load;
-assign load = req;
-
-cy_psoc3_dp #(.cy_dpconfig(
-{
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM0:    */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM1:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM2:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM3:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM4:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM5:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM6:     */
-	`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-	`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-	`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-	`CS_CMP_SEL_CFGA, /*CFGRAM7:     */
-	8'hFF, 8'h00,	/*CFG9:     */
-	8'hFF, 8'hFF,	/*CFG11-10:     */
-	`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
-	`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
-	`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
-	`SC_SI_A_DEFSI, /*CFG13-12:     */
-	`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
-	1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
-	`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
-	`SC_FB_NOCHN, `SC_CMP1_NOCHN,
-	`SC_CMP0_NOCHN, /*CFG15-14:     */
-	10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
-	`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
-	`SC_WRK16CAT_DSBL /*CFG17-16:     */
-}
-)) dp(
-	/* input          */ .clk(clk),
-	/* input [02:00]  */ .cs_addr(3'b0),    // Program counter
-	/* input          */ .route_si(1'b0),   // Shift in
-	/* input          */ .route_ci(1'b0),   // Carry in
-	/* input          */ .f0_load(load),    // Load FIFO 0
-	/* input          */ .f1_load(1'b0), 	// Load FIFO 1
-	/* input          */ .d0_load(1'b0), 	// Load Data Register 0
-	/* input          */ .d1_load(1'b0), 	// Load Data Register 1
-	/* output         */ .ce0(), 			// Accumulator 0 = Data register 0
-	/* output         */ .cl0(), 			// Accumulator 0 < Data register 0
-	/* output         */ .z0(), 			// Accumulator 0 = 0
-	/* output         */ .ff0(), 			// Accumulator 0 = FF
-	/* output         */ .ce1(), 			// Accumulator [0|1] = Data register 1
-	/* output         */ .cl1(), 			// Accumulator [0|1] < Data register 1
-	/* output         */ .z1(), 			// Accumulator 1 = 0
-	/* output         */ .ff1(), 			// Accumulator 1 = FF
-	/* output         */ .ov_msb(), 		// Operation over flow
-	/* output         */ .co_msb(), 		// Carry out
-	/* output         */ .cmsb(), 			// Carry out
-	/* output         */ .so(), 			// Shift out
-    /* output         */ .f0_bus_stat(drq), // not empty
-	/* output         */ .f0_blk_stat(full),// full
-	/* output         */ .f1_bus_stat(), 	// FIFO 1 status to uP
-	/* output         */ .f1_blk_stat(), 	// FIFO 1 status to DP
-	/* input          */ .ci(1'b0), 		// Carry in from previous stage
-	/* output         */ .co(), 			// Carry out to next stage
-	/* input          */ .sir(1'b0), 		// Shift in from right side
-	/* output         */ .sor(), 			// Shift out to right side
-	/* input          */ .sil(1'b0), 		// Shift in from left side
-	/* output         */ .sol(), 			// Shift out to left side
-	/* input          */ .msbi(1'b0), 		// MSB chain in
-	/* output         */ .msbo(), 			// MSB chain out
-	/* input [01:00]  */ .cei(2'b0),        // Compare equal in from prev stage
-	/* output [01:00] */ .ceo(),            // Compare equal out to next stage
-	/* input [01:00]  */ .cli(2'b0), 	    // Compare less than in from prv stage
-	/* output [01:00] */ .clo(),            // Compare less than out to next stage
-	/* input [01:00]  */ .zi(2'b0),         // Zero detect in from previous stage
-	/* output [01:00] */ .zo(),             // Zero detect out to next stage
-	/* input [01:00]  */ .fi(2'b0), 		// 0xFF detect in from previous stage
-	/* output [01:00] */ .fo(), 	        // 0xFF detect out to next stage
-	/* input [01:00]  */ .capi(2'b0),	    // Capture in from previous stage
-	/* output [01:00] */ .capo(),		    // Capture out to next stage
-	/* input          */ .cfbi(1'b0), 		// CRC Feedback in from previous stage
-	/* output         */ .cfbo(), 			// CRC Feedback out to next stage
-	/* input [07:00]  */ .pi(pi), 		    // Parallel data port
-	/* output [07:00] */ .po()              // Parallel data port
-);
-
-//`#end` -- edit above this line, do not edit this line
-endmodule
-//`#start footer` -- edit after this line, do not edit this line
-//`#end` -- edit above this line, do not edit this line
-
-
-
-
--- a/FluxEngine.cydsn/FIFOout/API/c.c
+++ b/FluxEngine.cydsn/FIFOout/API/c.c
@@ -1,27 +0,0 @@
-#include "cyfitter_cfg.h"
-#include "cydevice_trm.h"
-#include "cyfitter.h"
-#include "`$INSTANCE_NAME`_h.h"
-
-void `$INSTANCE_NAME`_Start()
-{
-   `$INSTANCE_NAME`_Init();
-}    
-
-void `$INSTANCE_NAME`_Stop()
-{
-    `$INSTANCE_NAME`_Disable();
-}
-
-void `$INSTANCE_NAME`_Init()
-{    
-    `$INSTANCE_NAME`_Enable();
-    
-}
-void `$INSTANCE_NAME`_Enable()
-{
-}
-
-void `$INSTANCE_NAME`_Disable()
-{
-}
--- a/FluxEngine.cydsn/FIFOout/API/h.h
+++ b/FluxEngine.cydsn/FIFOout/API/h.h
@@ -1,50 +0,0 @@
-#if !defined(`$INSTANCE_NAME`_H)
-#define `$INSTANCE_NAME`_H
-
-#include "cytypes.h"
-#include "cyfitter.h"
-#include "CyLib.h" 
-
-#define `$INSTANCE_NAME`_FIFO_PTR	         ((reg8 *) `$INSTANCE_NAME`_dp__F0_REG)
-
-    /* Macros to clear DP FIFOs.*/
-#define `$INSTANCE_NAME`_CLEAR do { \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)));\
-    } while(0)
-
-/* Macros to set FIFO level mode. See the TRM for details */
-#define `$INSTANCE_NAME`_SET_LEVEL_NORMAL \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfbu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-#define `$INSTANCE_NAME`_SET_LEVEL_MID \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x04u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-
-/* Macros to set FIFO to single-buffer mode. */
-#define `$INSTANCE_NAME`_SINGLE_BUFFER_SET \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0x01u | \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-
-/* Macros to return the FIFO to normal mode. */
-#define `$INSTANCE_NAME`_SINGLE_BUFFER_UNSET \
-    CY_SET_XTND_REG8(\
-        ((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG), 0xfeu & \
-        CY_GET_XTND_REG8(((reg8 *) `$INSTANCE_NAME`_dp__DP_AUX_CTL_REG)))
-    
-void `$INSTANCE_NAME`_Enable();
-void `$INSTANCE_NAME`_Disable();
-void `$INSTANCE_NAME`_Start();
-void `$INSTANCE_NAME`_Stop();
-void `$INSTANCE_NAME`_Init();
-
-#endif
-
-/* [] END OF FILE */
--- a/FluxEngine.cydsn/FIFOout/FIFOout.cysym
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.cysym
--- a/FluxEngine.cydsn/FIFOout/FIFOout.v
+++ b/FluxEngine.cydsn/FIFOout/FIFOout.v
@@ -1,168 +0,0 @@
-
-//`#start header` -- edit after this line, do not edit this line
-`include "cypress.v"
-//`#end` -- edit above this line, do not edit this line
-// Generated on 11/16/2017 at 15:44
-// Component: FIFOout
-module FIFOout (
-    input req,
-	input clk,
-    output [7:0] d,
-	output drq,
-	output empty,
-    output ack
-);
-
-//`#start body` -- edit after this line, do not edit this line
-
-/* Reads from the FIFO are done based on the FIFO being not empty. */
- 
-wire [7:0] po;
-assign d = po;
-
-localparam STATE_WAIT = 1'b0;
-localparam STATE_READ = 1'b1;
-
-reg state;
-reg oldreq;
-
-assign ack = (state != STATE_READ);
-
-always @(posedge clk)
-begin
-    case (state)
-        STATE_WAIT:
-        begin
-            if (!empty)
-            begin
-                if (req && !oldreq)
-                begin
-                    state <= STATE_READ;
-                end
-                oldreq <= req;
-            end
-        end
-        
-        STATE_READ:
-        begin
-            state <= STATE_WAIT;
-        end
-    endcase
-end
-            
-cy_psoc3_dp #(.cy_dpconfig(
-{
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM2:           */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM3:           */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM4:           */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM5:           */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM6:           */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM7:           */
-    8'hFF, 8'h00,  /*CFG9:           */
-    8'hFF, 8'hFF,  /*CFG11-10:           */
-    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
-    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
-    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
-    `SC_SI_A_DEFSI, /*CFG13-12:           */
-    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
-    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
-    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
-    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
-    `SC_CMP0_NOCHN, /*CFG15-14:           */
-    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
-    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
-    `SC_WRK16CAT_DSBL /*CFG17-16:           */
-}
-)) dp(
-        /*  input                   */  .reset(1'b0),
-        /*  input                   */  .clk(clk),
-        /*  input   [02:00]         */  .cs_addr({2'b0, state}),
-        /*  input                   */  .route_si(1'b0),
-        /*  input                   */  .route_ci(1'b0),
-        /*  input                   */  .f0_load(1'b0),
-        /*  input                   */  .f1_load(1'b0),
-        /*  input                   */  .d0_load(1'b0),
-        /*  input                   */  .d1_load(1'b0),
-        /*  output                  */  .ce0(),
-        /*  output                  */  .cl0(),
-        /*  output                  */  .z0(),
-        /*  output                  */  .ff0(),
-        /*  output                  */  .ce1(),
-        /*  output                  */  .cl1(),
-        /*  output                  */  .z1(),
-        /*  output                  */  .ff1(),
-        /*  output                  */  .ov_msb(),
-        /*  output                  */  .co_msb(),
-        /*  output                  */  .cmsb(),
-        /*  output                  */  .so(),
-        /*  output                  */  .f0_bus_stat(drq), // not full
-        /*  output                  */  .f0_blk_stat(empty), // empty
-        /*  output                  */  .f1_bus_stat(),
-        /*  output                  */  .f1_blk_stat(),
-        
-        /* input                    */  .ci(1'b0),     // Carry in from previous stage
-        /* output                   */  .co(),// Carry out to next stage
-        /* input                    */  .sir(1'b0),    // Shift in from right side
-        /* output                   */  .sor(),        // Shift out to right side
-        /* input                    */  .sil(1'b0),    // Shift in from left side
-        /* output                   */  .sol(),        // Shift out to left side
-        /* input                    */  .msbi(1'b0),   // MSB chain in
-        /* output                   */  .msbo(),       // MSB chain out
-        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
-        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
-        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
-        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
-        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
-        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
-        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
-        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
-        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
-        /* output [01:00]           */  .capo(),       // Software capture to next stage
-        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
-        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
-        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
-        /* output [07:00]           */  .po(po)       // Parallel data port
-);
-
-//`#end` -- edit above this line, do not edit this line
-endmodule
-//`#start footer` -- edit after this line, do not edit this line
-//`#end` -- edit above this line, do not edit this line
-
-
-
-
-
-
-
-
-
-
-
-
--- a/FluxEngine.cydsn/FluxEngine.cydwr
+++ b/FluxEngine.cydsn/FluxEngine.cydwr
@@ -28,54 +28,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_DIVIDER" />
-        <Data key="desired_freq" value="0" />
-        <Data key="desired_unit" value="15" />
-        <Data key="divider" value="0" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="Clock_5" />
-        <Data key="named_src_direct_connect" value="True" />
-        <Data key="netlist_name" value="Clock_5" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
-        <Data key="src_clk_name" value="BUS_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
-      <Group key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_DIVIDER" />
-        <Data key="desired_freq" value="0" />
-        <Data key="desired_unit" value="15" />
-        <Data key="divider" value="0" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="Clock_8" />
-        <Data key="named_src_direct_connect" value="True" />
-        <Data key="netlist_name" value="Clock_8" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
-        <Data key="src_clk_name" value="BUS_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -195,54 +147,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="71bc291d-84a7-40a8-b7b2-1c8a34326a31">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_FREQ" />
-        <Data key="desired_freq" value="300" />
-        <Data key="desired_unit" value="0" />
-        <Data key="divider" value="65536" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="CLOCK300" />
-        <Data key="named_src_direct_connect" value="False" />
-        <Data key="netlist_name" value="CLOCK300" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
-        <Data key="src_clk_name" value="IMO" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
-      <Group key="90ce0c72-9f10-44ef-a049-f0f525d59bea">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_FREQ" />
-        <Data key="desired_freq" value="128" />
-        <Data key="desired_unit" value="0" />
-        <Data key="divider" value="65536" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="CLOCK8" />
-        <Data key="named_src_direct_connect" value="False" />
-        <Data key="netlist_name" value="CLOCK8" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="CEF43CFB-0213-49b9-B980-2FFAB81C5B47" />
-        <Data key="src_clk_name" value="IMO" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="349ffa20-8576-4ac3-9a6f-34ef606de6cf">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -266,29 +170,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a">
-        <Data key="check_tolerance" value="False" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="AUTO" />
-        <Data key="desired_freq" value="1600000" />
-        <Data key="desired_unit" value="0" />
-        <Data key="divider" value="40" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="OUTPUT_VOLTAGE_ADC_theACLK" />
-        <Data key="netlist_name" value="\OUTPUT_VOLTAGE_ADC:theACLK\" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
-        <Data key="src_clk_name" value="MASTER_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="6616e828-6611-4893-a674-66c861d79d6c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -360,53 +241,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="09974428-e912-491f-8d2f-361ba50e7599">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_DIVIDER" />
-        <Data key="desired_freq" value="0" />
-        <Data key="desired_unit" value="15" />
-        <Data key="divider" value="0" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="Clock_6" />
-        <Data key="named_src_direct_connect" value="True" />
-        <Data key="netlist_name" value="Clock_6" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
-        <Data key="src_clk_name" value="BUS_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
-      <Group key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a">
-        <Data key="check_tolerance" value="False" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="AUTO" />
-        <Data key="desired_freq" value="1600000" />
-        <Data key="desired_unit" value="0" />
-        <Data key="divider" value="40" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="INPUT_VOLTAGE_ADC_theACLK" />
-        <Data key="netlist_name" value="\INPUT_VOLTAGE_ADC:theACLK\" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="61737EF6-3B74-48f9-8B91-F7473A442AE7" />
-        <Data key="src_clk_name" value="MASTER_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="b762c287-7f87-4b21-982e-84be01dc5115">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -454,30 +288,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="b722443b-8f81-46dc-bf9b-c95eb62bc181">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_DIVIDER" />
-        <Data key="desired_freq" value="0" />
-        <Data key="desired_unit" value="15" />
-        <Data key="divider" value="0" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="Clock_1" />
-        <Data key="named_src_direct_connect" value="True" />
-        <Data key="netlist_name" value="Clock_1" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
-        <Data key="src_clk_name" value="BUS_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -502,30 +312,6 @@
        <Data key="sync_with_bus_clk" value="True" />
        <Data key="user_set_domain" value="False" />
      </Group>
-      <Group key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f">
-        <Data key="check_tolerance" value="True" />
-        <Data key="clock_version" value="v1" />
-        <Data key="derive_type" value="NAMED_DIVIDER" />
-        <Data key="desired_freq" value="0" />
-        <Data key="desired_unit" value="15" />
-        <Data key="divider" value="0" />
-        <Data key="domain" value="DIGITAL" />
-        <Data key="enabled" value="True" />
-        <Data key="minus_accuracy" value="0.25" />
-        <Data key="minus_tolerance" value="5" />
-        <Data key="name" value="Clock_7" />
-        <Data key="named_src_direct_connect" value="True" />
-        <Data key="netlist_name" value="Clock_7" />
-        <Data key="placement" value="AUTO" />
-        <Data key="plus_accuracy" value="0.25" />
-        <Data key="plus_tolerance" value="5" />
-        <Data key="scope" value="LOCAL" />
-        <Data key="src_clk_id" value="75C2148C-3656-4d8a-846D-0CAE99AB6FF7" />
-        <Data key="src_clk_name" value="BUS_CLK" />
-        <Data key="start_on_reset" value="True" />
-        <Data key="sync_with_bus_clk" value="True" />
-        <Data key="user_set_domain" value="False" />
-      </Group>
      <Group key="e4a53a4c-40e1-4747-a72a-10193ffdf31c">
        <Data key="check_tolerance" value="True" />
        <Data key="clock_version" value="v1" />
@@ -823,27 +609,18 @@
  <Group key="DWRInstGuidMapping">
    <Group key="Clock">
      <Data key="0b2f9bbb-00ce-4115-a788-ffb9d046a9e5" value="Clock_4" />
-      <Data key="1a7e8637-3b6b-4e84-839c-0dfc18fdaf5b" value="Clock_5" />
-      <Data key="3f3708ae-fb62-4012-919b-9a3b9a1dfbc2" value="Clock_8" />
      <Data key="4eef02b9-8ad1-43c4-85f1-b3335faa5fc4" value="Clock_3" />
      <Data key="06c4d5d4-f15f-4b29-a1d0-c24b2e38b1ec" value="CounterClock" />
      <Data key="24cd38f7-f472-4403-837f-86807c8f5333" value="PULSE_CLOCK" />
      <Data key="63ed4137-0b09-4256-8a27-35c9a2653f1a" value="Clock_2" />
      <Data key="66f14071-bddd-4b4d-a9aa-a129cceaa7b6" value="Clock_3" />
-      <Data key="71bc291d-84a7-40a8-b7b2-1c8a34326a31" value="CLOCK300" />
-      <Data key="90ce0c72-9f10-44ef-a049-f0f525d59bea" value="CLOCK8" />
      <Data key="349ffa20-8576-4ac3-9a6f-34ef606de6cf" value="Clock_1" />
-      <Data key="4033c29d-f4bc-4e94-ac95-aa587e869f88/696a0979-21fc-4185-bf38-6c79febcde7a" value="OUTPUT_VOLTAGE_ADC_theACLK" />
      <Data key="6616e828-6611-4893-a674-66c861d79d6c" value="SignalSamplingClock" />
      <Data key="12664fc6-9d70-44b1-8a49-887a292e1b7f" value="Clock_3" />
      <Data key="75187c05-9501-4450-b306-6ccdd3bb77db" value="Clock_5" />
-      <Data key="09974428-e912-491f-8d2f-361ba50e7599" value="Clock_6" />
-      <Data key="a5825a94-fa18-4e4f-a843-bc687cacbd56/696a0979-21fc-4185-bf38-6c79febcde7a" value="INPUT_VOLTAGE_ADC_theACLK" />
      <Data key="b762c287-7f87-4b21-982e-84be01dc5115" value="Clock_2" />
      <Data key="b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358" value="UART_IntClock" />
-      <Data key="b722443b-8f81-46dc-bf9b-c95eb62bc181" value="Clock_1" />
      <Data key="cb7e877c-9fb4-4fc1-a708-f1e48eb5a68c" value="CounterClock" />
-      <Data key="d3075dc6-05c8-4dc9-9959-cf7014c0e66f" value="Clock_7" />
      <Data key="e4a53a4c-40e1-4747-a72a-10193ffdf31c" value="Clock_1" />
      <Data key="efd5f185-0c32-4824-ba72-3ceb5356f5a7" value="Clock_1" />
    </Group>
@@ -861,18 +638,16 @@
      <Data key="a5d987c6-e45b-45b9-ad93-656fab06d720" value="TRK00" />
      <Data key="a93ef5b3-00f4-42c0-8fad-0e275a7e2537" value="MOTEB" />
      <Data key="b8380fb7-fdb8-449f-bd8d-c4ca96cdf55a" value="DEBUG_PINS" />
-      <Data key="bc2e8987-db82-469c-bf6f-22fd3464cc70" value="DEBUG_PINS" />
      <Data key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f" value="DEBUG_PINS" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c" value="USBFS_Dm" />
      <Data key="beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42" value="USBFS_Dp" />
      <Data key="c5367cde-21d5-4866-9a32-d16abfea0c61" value="WPT" />
      <Data key="d19368c5-6855-41bb-a9ff-808938abef00" value="INDEX" />
      <Data key="e9f14b5a-b2bf-49b8-98f3-d7b5a43ace8d" value="DRVSB" />
-      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="INDEX300" />
+      <Data key="e851a3b9-efb8-48be-bbb8-b303b216c393" value="LED" />
      <Data key="e51063a9-4fad-40c7-a06b-7cc4b137dc18" value="DSKCHG" />
      <Data key="ea7ee228-8b3f-426c-8bb8-cd7a81937769" value="DIR" />
      <Data key="ed092b9b-d398-4703-be89-cebf998501f6" value="UartTx" />
-      <Data key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663" value="INDEX360" />
      <Data key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6" value="UART_tx" />
      <Data key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b" value="DRVSA" />
      <Data key="fff78075-035e-43d7-8577-bc5be4d21926" value="WGATE" />
@@ -4084,32 +3859,6 @@
        <Data key="Port Format" value="2,3" />
      </Group>
    </Group>
-    <Group key="bc2e8987-db82-469c-bf6f-22fd3464cc70">
-      <Group key="0">
-        <Data key="Port Format" value="0,0" />
-      </Group>
-      <Group key="1">
-        <Data key="Port Format" value="0,1" />
-      </Group>
-      <Group key="2">
-        <Data key="Port Format" value="0,2" />
-      </Group>
-      <Group key="3">
-        <Data key="Port Format" value="0,3" />
-      </Group>
-      <Group key="4">
-        <Data key="Port Format" value="0,4" />
-      </Group>
-      <Group key="5">
-        <Data key="Port Format" value="0,5" />
-      </Group>
-      <Group key="6">
-        <Data key="Port Format" value="0,6" />
-      </Group>
-      <Group key="7">
-        <Data key="Port Format" value="0,7" />
-      </Group>
-    </Group>
    <Group key="bc5d52a1-1b25-4aa0-9ba9-3f81d122772f">
      <Group key="0">
        <Data key="Port Format" value="0,5" />
@@ -4145,7 +3894,7 @@
    </Group>
    <Group key="e851a3b9-efb8-48be-bbb8-b303b216c393">
      <Group key="0">
-        <Data key="Port Format" value="3,0" />
+        <Data key="Port Format" value="2,1" />
      </Group>
    </Group>
    <Group key="e51063a9-4fad-40c7-a06b-7cc4b137dc18">
@@ -4163,14 +3912,9 @@
        <Data key="Port Format" value="12,7" />
      </Group>
    </Group>
-    <Group key="f9a7371a-8a7d-4144-8b08-69e3d2a3a663">
-      <Group key="0">
-        <Data key="Port Format" value="3,1" />
-      </Group>
-    </Group>
    <Group key="fbd1f839-40f9-498e-a48b-5f3048ea5c3d/52f31aa9-2f0a-497d-9a1f-1424095e13e6">
      <Group key="0">
-        <Data key="Port Format" value="12,7" />
+        <Data key="Port Format" value="2,5" />
      </Group>
    </Group>
    <Group key="fede1767-f3fd-4021-b3d7-8f9d88f36f9b">
--- a/FluxEngine.cydsn/FluxEngine.cyprj
+++ b/FluxEngine.cydsn/FluxEngine.cyprj
--- a/FluxEngine.cydsn/Sampler/Sampler.v
+++ b/FluxEngine.cydsn/Sampler/Sampler.v
@@ -1,134 +0,0 @@
-
-//`#start header` -- edit after this line, do not edit this line
-`include "cypress.v"
-`include "../SuperCounter/SuperCounter.v"
-
-//`#end` -- edit above this line, do not edit this line
-// Generated on 12/11/2019 at 21:18
-// Component: Sampler
-module Sampler (
-	output [2:0] debug_state,
-	output reg [7:0] opcode,
-	output  req,
-	input   clock,
-	input   index,
-	input   rdata,
-	input   reset,
-	input   sampleclock
-);
-
-//`#start body` -- edit after this line, do not edit this line
-
-localparam STATE_RESET = 0;
-localparam STATE_WAITING = 1;
-localparam STATE_INTERVAL = 2;
-localparam STATE_DISPATCH = 3;
-localparam STATE_OPCODE = 4;
-localparam STATE_COUNTING = 5;
-
-reg [2:0] state;
-wire [6:0] counter;
-
-wire countnow;
-assign countnow = (state == STATE_COUNTING);
-
-wire counterreset;
-assign counterreset = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
-
-SuperCounter #(.Delta(1), .ResetValue(0)) Counter
-(
-    /* input */ .clk(clock),
-    /* input */ .reset(counterreset),
-    /* input */ .count(countnow),
-    /* output */ .d(counter)
-);
-
-reg oldsampleclock;
-wire sampleclocked;
-assign sampleclocked = !oldsampleclock && sampleclock;
-
-reg oldindex;
-wire indexed;
-assign indexed = !oldindex && index;
-
-wire rdataed;
-reg oldrdata;
-assign rdataed = !oldrdata && rdata;
-
-assign req = (state == STATE_INTERVAL) || (state == STATE_OPCODE);
-
-always @(posedge clock)
-begin
-    if (reset)
-    begin
-        state <= STATE_RESET;
-        opcode <= 0;
-        oldsampleclock <= 0;
-        oldindex <= 0;
-        oldrdata <= 0;
-    end
-    else
-        case (state)
-            STATE_RESET:
-                state <= STATE_WAITING;
-            
-            STATE_WAITING:
-            begin
-                if (rdataed || indexed)
-                begin
-                    opcode <= {0, counter};
-                    state <= STATE_INTERVAL;
-                end
-                else if (sampleclocked)
-                begin
-                    oldsampleclock <= 1;
-                    if (counter == 7'h7f)
-                    begin
-                        opcode <= {0, counter};
-                        state <= STATE_OPCODE;
-                    end
-                    else
-                        state <= STATE_COUNTING;
-                end
-                
-                if (oldrdata && !rdata)
-                    oldrdata <= 0;
-                if (oldindex && !index)
-                    oldindex <= 0;
-                if (oldsampleclock && !sampleclock)
-                    oldsampleclock <= 0;
-            end
-            
-            STATE_INTERVAL: /* interval byte sent here; counter reset */
-                state <= STATE_DISPATCH;
-                
-            STATE_DISPATCH: /* relax after interval byte, dispatch for opcode */
-            begin
-                if (rdataed)
-                begin
-                    oldrdata <= 1;
-                    opcode <= 8'h80;
-                    state <= STATE_OPCODE;
-                end
-                else if (indexed)
-                begin
-                    oldindex <= 1;
-                    opcode <= 8'h81;
-                    state <= STATE_OPCODE;
-                end
-                else
-                    state <= STATE_WAITING;
-            end
-            
-            STATE_OPCODE: /* opcode byte sent here */
-                state <= STATE_WAITING;
-                            
-            STATE_COUNTING: /* counter changes here */
-                state <= STATE_WAITING;
-        endcase
-end
-
-//`#end` -- edit above this line, do not edit this line
-endmodule
-//`#start footer` -- edit after this line, do not edit this line
-//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/Sequencer/Sequencer.v
+++ b/FluxEngine.cydsn/Sequencer/Sequencer.v
@@ -1,103 +0,0 @@
-
-//`#start header` -- edit after this line, do not edit this line
-`include "cypress.v"
-//`#end` -- edit above this line, do not edit this line
-// Generated on 11/24/2019 at 17:25
-// Component: Sequencer
-module Sequencer (
-	output req, /* request new data on leading edge */
-	output wdata,
-    output [2:0] debug_state,
-	input clock,
-	input dataclock, /* incoming data on leading edge */
-	input [7:0] opcode,
-    input index,
-    input sampleclock,
-    input reset
-);
-
-//`#start body` -- edit after this line, do not edit this line
-
-localparam STATE_IDLE = 0;
-localparam STATE_LOAD = 1;
-localparam STATE_WAITING = 2;
-localparam STATE_PULSING = 3;
-localparam STATE_INDEXING = 4;
-
-localparam OPCODE_PULSE = 8'h80;
-localparam OPCODE_INDEX = 8'h81;
-
-reg [2:0] state;
-reg [6:0] countdown;
-
-assign req = (state == STATE_LOAD);
-assign wdata = (state == STATE_PULSING);
-assign debug_state = state;
-
-reg olddataclock;
-wire dataclocked;
-always @(posedge clock) olddataclock <= dataclock;
-assign dataclocked = !olddataclock && dataclock;
-
-reg oldsampleclock;
-wire sampleclocked;
-always @(posedge clock) oldsampleclock <= sampleclock;
-assign sampleclocked = !oldsampleclock && sampleclock;
-
-reg oldindex;
-wire indexed;
-always @(posedge clock) oldindex <= index;
-assign indexed = !oldindex && index;
-
-always @(posedge clock)
-begin
-    if (reset)
-    begin
-        state <= STATE_IDLE;
-        countdown <= 0;
-    end
-    else
-        case (state)
-            STATE_IDLE:
-                state <= STATE_LOAD;
-            
-            STATE_LOAD:
-                if (dataclocked)
-                    case (opcode)
-                        OPCODE_PULSE:
-                            state <= STATE_PULSING;
-                        
-                        OPCODE_INDEX:
-                            state <= STATE_INDEXING;
-                        
-                        default:
-                        begin
-                            countdown <= opcode[6:0];
-                            state <= STATE_WAITING;
-                        end
-                    endcase
-            
-            STATE_WAITING:
-                if (sampleclocked)
-                begin
-                    if (countdown == 0)
-                        state <= STATE_LOAD;
-                    else
-                        countdown <= countdown - 1;
-                end
-            
-            STATE_PULSING:
-                state <= STATE_LOAD;
-            
-            STATE_INDEXING:
-                if (indexed)
-                    state <= STATE_LOAD;
-                else
-                    state <= STATE_INDEXING;
-        endcase
-end
-
-//`#end` -- edit above this line, do not edit this line
-endmodule
-//`#start footer` -- edit after this line, do not edit this line
-//`#end` -- edit above this line, do not edit this line
--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.cysym
--- a/FluxEngine.cydsn/SuperCounter/SuperCounter.v
+++ b/FluxEngine.cydsn/SuperCounter/SuperCounter.v
@@ -1,156 +0,0 @@
-
-//`#start header` -- edit after this line, do not edit this line
-`include "cypress.v"
-//`#end` -- edit above this line, do not edit this line
-// Generated on 11/16/2017 at 15:44
-// Component: FIFOout
-module SuperCounter (
-	input clk,
-    input reset,
-    input count,
-    output [7:0] d,
-	output drq,
-	output empty,
-    output ack
-);
-
-//`#start body` -- edit after this line, do not edit this line
-
-parameter ResetValue = 0;
-parameter Delta = 1;
-    
-wire [7:0] po;
-assign d = po;
-
-localparam STATE_RESET = 0;
-localparam STATE_WAIT = 1;
-localparam STATE_ADD = 2;
-
-reg oldcount;
-wire counted;
-assign counted = count && !oldcount;
-
-always @(posedge clk) oldcount <= count;
-
-wire [2:0] cs;
-assign cs = reset ? STATE_RESET : (counted ? STATE_ADD : STATE_WAIT);
-            
-cy_psoc3_dp #(.d0_init(ResetValue), .d1_init(Delta), 
-.cy_dpconfig(
-{
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM0:  STATE_RESET*/
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM1:  STATE_WAIT*/
-    `CS_ALU_OP__ADD, `CS_SRCA_A0, `CS_SRCB_D1,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM2:  STATE_ADD*/
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM3:             */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM4:             */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM5:             */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM6:             */
-    `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
-    `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
-    `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM7:             */
-    8'hFF, 8'h00,  /*CFG9:             */
-    8'hFF, 8'hFF,  /*CFG11-10:             */
-    `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
-    `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
-    `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
-    `SC_SI_A_DEFSI, /*CFG13-12:             */
-    `SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
-    1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
-    `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
-    `SC_FB_NOCHN, `SC_CMP1_NOCHN,
-    `SC_CMP0_NOCHN, /*CFG15-14:             */
-    10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
-    `SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
-    `SC_WRK16CAT_DSBL /*CFG17-16:             */
-}
-)) dp(
-        /*  input                   */  .reset(1'b0),
-        /*  input                   */  .clk(clk),
-        /*  input   [02:00]         */  .cs_addr(cs),
-        /*  input                   */  .route_si(1'b0),
-        /*  input                   */  .route_ci(1'b0),
-        /*  input                   */  .f0_load(1'b0),
-        /*  input                   */  .f1_load(1'b0),
-        /*  input                   */  .d0_load(1'b0),
-        /*  input                   */  .d1_load(1'b0),
-        /*  output                  */  .ce0(),
-        /*  output                  */  .cl0(),
-        /*  output                  */  .z0(),
-        /*  output                  */  .ff0(),
-        /*  output                  */  .ce1(),
-        /*  output                  */  .cl1(),
-        /*  output                  */  .z1(),
-        /*  output                  */  .ff1(),
-        /*  output                  */  .ov_msb(),
-        /*  output                  */  .co_msb(),
-        /*  output                  */  .cmsb(),
-        /*  output                  */  .so(),
-        /*  output                  */  .f0_bus_stat(),
-        /*  output                  */  .f0_blk_stat(),
-        /*  output                  */  .f1_bus_stat(),
-        /*  output                  */  .f1_blk_stat(),
-        
-        /* input                    */  .ci(1'b0),     // Carry in from previous stage
-        /* output                   */  .co(),// Carry out to next stage
-        /* input                    */  .sir(1'b0),    // Shift in from right side
-        /* output                   */  .sor(),        // Shift out to right side
-        /* input                    */  .sil(1'b0),    // Shift in from left side
-        /* output                   */  .sol(),        // Shift out to left side
-        /* input                    */  .msbi(1'b0),   // MSB chain in
-        /* output                   */  .msbo(),       // MSB chain out
-        /* input [01:00]            */  .cei(2'b0),    // Compare equal in from prev stage
-        /* output [01:00]           */  .ceo(),        // Compare equal out to next stage
-        /* input [01:00]            */  .cli(2'b0),    // Compare less than in from prv stage
-        /* output [01:00]           */  .clo(),        // Compare less than out to next stage
-        /* input [01:00]            */  .zi(2'b0),     // Zero detect in from previous stage
-        /* output [01:00]           */  .zo(),         // Zero detect out to next stage
-        /* input [01:00]            */  .fi(2'b0),     // 0xFF detect in from previous stage
-        /* output [01:00]           */  .fo(),         // 0xFF detect out to next stage
-        /* input [01:00]            */  .capi(2'b0),   // Software capture from previous stage
-        /* output [01:00]           */  .capo(),       // Software capture to next stage
-        /* input                    */  .cfbi(1'b0),   // CRC Feedback in from previous stage
-        /* output                   */  .cfbo(),       // CRC Feedback out to next stage
-        /* input [07:00]            */  .pi(8'b0),     // Parallel data port
-        /* output [07:00]           */  .po(po)       // Parallel data port
-);
-
-//`#end` -- edit above this line, do not edit this line
-endmodule
-//`#start footer` -- edit after this line, do not edit this line
-//`#end` -- edit above this line, do not edit this line
-
-
-
-
-
-
-
-
-
-
-
-
-
-
--- a/FluxEngine.cydsn/TopDesign/TopDesign.cysch
+++ b/FluxEngine.cydsn/TopDesign/TopDesign.cysch
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cysym
--- a/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
+++ b/FluxEngine.cydsn/UdbSampler/UdbSampler.cyudb
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cysym
--- a/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
+++ b/FluxEngine.cydsn/UdbSequencer/UdbSequencer.cyudb
--- a/FluxEngine.cydsn/main.c
+++ b/FluxEngine.cydsn/main.c
@@ -17,14 +17,14 @@
 #define STEP_TOWARDS0 1
 #define STEP_AWAYFROM0 0

-static volatile uint32_t clock = 0; /* ms */
+static volatile uint32_t clock = 0;
 static volatile bool index_irq = false;

 static bool motor_on = false;
 static uint32_t motor_on_time = 0;
 static bool homed = false;
 static int current_track = 0;
-static struct set_drive_frame current_drive_flags;
+static uint8_t current_drive_flags = 0;

 #define BUFFER_COUNT 16
 #define BUFFER_SIZE 64
@@ -45,21 +45,6 @@ static void system_timer_cb(void)
 {
    CyGlobalIntDisable;
    clock++;
-    
-    static int counter300rpm = 0;
-    counter300rpm++;
-    if (counter300rpm == 200)
-        counter300rpm = 0;
-    
-    static int counter360rpm = 0;
-    counter360rpm++;
-    if (counter360rpm == 167)
-        counter360rpm = 0;
-    
-    FAKE_INDEX_GENERATOR_REG_Write(
-        ((counter300rpm == 0) ? 1 : 0)
-        | ((counter360rpm == 0) ? 2 : 0));
-    
    CyGlobalIntEnable;
 }

@@ -100,22 +85,10 @@ static void print(const char* msg, ...)
    UART_PutCRLF();
 }

-static void set_drive_flags(struct set_drive_frame* flags)
-{
-    if (current_drive_flags.drive != flags->drive)
-        homed = false;
-    
-    current_drive_flags = *flags;
-    DRIVESELECT_REG_Write(flags->drive ? 2 : 1); /* select drive 1 or 0 */
-    DENSITY_REG_Write(flags->high_density); /* density bit */
-    INDEX_REG_Write(flags->index_mode);
-}
-
 static void start_motor(void)
 {
    if (!motor_on)
    {
-        set_drive_flags(&current_drive_flags);
        MOTOR_REG_Write(1);
        CyDelay(1000);
        homed = false;
@@ -126,16 +99,6 @@ static void start_motor(void)
    CyWdtClear();
 }

-static void stop_motor(void)
-{
-    if (motor_on)
-    {
-        MOTOR_REG_Write(0);
-        DRIVESELECT_REG_Write(0); /* deselect all drives */
-        motor_on = false;
-    }
-}
-
 static void wait_until_writeable(int ep)
 {
    while (USBFS_GetEPState(ep) != USBFS_IN_BUFFER_EMPTY)
@@ -175,36 +138,25 @@ static void cmd_get_version(struct any_frame* f)

 static void step(int dir)
 {
-    STEP_REG_Write(dir); /* step high */
-    CyDelayUs(6);
-    STEP_REG_Write(dir | 2); /* step low */
-    CyDelayUs(6);
-    STEP_REG_Write(dir); /* step high again, drive moves now */
+    STEP_REG_Write(dir);
+    CyDelayUs(1);
+    STEP_REG_Write(dir | 2);
+    CyDelayUs(1);
+    STEP_REG_Write(dir);
    CyDelay(STEP_INTERVAL_TIME);
 }

-static void home(void)
-{
-    for (int i=0; i<100; i++)
-    {
-        /* Don't keep stepping forever, because if a drive's
-         * not connected bad things happen. */
-        if (TRACK0_REG_Read())
-            break;
-        step(STEP_TOWARDS0);
-    }
-    
-    /* Step to -1, which should be a nop, to reset the disk on disk change. */
-    step(STEP_TOWARDS0);
-}
-
 static void seek_to(int track)
 {
    start_motor();
-    if (!homed || (track == 0))
+    if (!homed)
    {
        print("homing");
-        home();
+        while (!TRACK0_REG_Read())
+            step(STEP_TOWARDS0);
+            
+        /* Step to -1, which should be a nop, to reset the disk on disk change. */
+        step(STEP_TOWARDS0);
        
        homed = true;
        current_track = 0;
@@ -215,7 +167,11 @@ static void seek_to(int track)
    while (track != current_track)
    {
        if (TRACK0_REG_Read())
+        {
+            if (current_track != 0)
+                print("unexpectedly detected track 0");
            current_track = 0;
+        }
        
        if (track > current_track)
        {
@@ -253,28 +209,16 @@ static void cmd_measure_speed(struct any_frame* f)
    start_motor();
    
    index_irq = false;
-    int start_clock = clock;
-    int elapsed = 0;
    while (!index_irq)
-    {
-        elapsed = clock - start_clock;
-        if (elapsed > 1000)
-        {
-            elapsed = 0;
-            break;
-        }
-    }
-
-    if (elapsed != 0)
-    {
-        index_irq = false;
-        start_clock = clock;
-        while (!index_irq)
-            elapsed = clock - start_clock;
-    }
+        ;
+    index_irq = false;
+    int start_clock = clock;
+    while (!index_irq)
+        ;
+    int end_clock = clock;
    
    DECLARE_REPLY_FRAME(struct speed_frame, F_FRAME_MEASURE_SPEED_REPLY);
-    r.period_ms = elapsed;
+    r.period_ms = end_clock - start_clock;
    send_reply((struct any_frame*) &r);    
 }

@@ -305,7 +249,7 @@ static void deinit_dma(void)

 static void init_capture_dma(void)
 {
-    dma_channel = SAMPLER_DMA_DmaInitialize(
+    dma_channel = CAPTURE_DMA_DmaInitialize(
        2 /* bytes */,
        true /* request per burst */, 
        HI16(CYDEV_PERIPH_BASE),
@@ -320,8 +264,8 @@ static void init_capture_dma(void)
            nexti = 0;

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],   
-            CY_DMA_TD_INC_DST_ADR | SAMPLER_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)SAMPLER_FIFO_FIFO_PTR), LO16((uint32)&dma_buffer[i]));
+            CY_DMA_TD_INC_DST_ADR | CAPTURE_DMA__TD_TERMOUT_EN);
+        CyDmaTdSetAddress(td[i], LO16((uint32)&SAMPLER_DATAPATH_F0_REG), LO16((uint32)&dma_buffer[i]));
    }    
 }

@@ -332,26 +276,26 @@ static void cmd_read(struct read_frame* f)
    
    /* Do slow setup *before* we go into the real-time bit. */
    
+    SAMPLER_CONTROL_Write(1); /* reset */
+    
    {
        uint8_t i = CyEnterCriticalSection();
-        SAMPLER_FIFO_SET_LEVEL_MID;
-        SAMPLER_FIFO_CLEAR;
-        SAMPLER_FIFO_SINGLE_BUFFER_UNSET;
+        SAMPLER_DATAPATH_F0_SET_LEVEL_MID;
+        SAMPLER_DATAPATH_F0_CLEAR;
+        SAMPLER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    
    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
    init_capture_dma();

-    /* Wait for the beginning of a rotation, if requested. */
+    /* Wait for the beginning of a rotation. */
        
-    if (f->synced)
-    {
-        index_irq = false;
-        while (!index_irq)
-            ;
-        index_irq = false;
-    }
+    print("wait");
+    index_irq = false;
+    while (!index_irq)
+        ;
+    index_irq = false;
    
    crunch_state_t cs = {};
    cs.outputptr = usb_buffer;
@@ -361,6 +305,8 @@ static void cmd_read(struct read_frame* f)
    dma_reading_from_td = -1;
    dma_underrun = false;
    int count = 0;
+    SAMPLER_CONTROL_Write(0); /* !reset */
+    CAPTURE_CONTROL_Write(1);
    CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
    CyDmaClearPendingDrq(dma_channel);
    CyDmaChEnable(dma_channel, 1);
@@ -368,27 +314,32 @@ static void cmd_read(struct read_frame* f)
    /* Wait for the first DMA transfer to complete, after which we can start the
     * USB transfer. */

-    while (dma_writing_to_td == 0)
+    while ((dma_writing_to_td == 0) && !index_irq)
        ;
    dma_reading_from_td = 0;
    
    /* Start transferring. */

-    uint32_t start_time = clock;
+    int revolutions = f->revolutions;
    while (!dma_underrun)
    {
        CyWdtClear();

+        /* Have we reached the index pulse? */
+        if (index_irq)
+        {
+            index_irq = false;
+            revolutions--;
+            if (revolutions == 0)
+                break;
+        }
+        
        /* Wait for the next block to be read. */
        while (dma_reading_from_td == dma_writing_to_td)
        {
            /* On an underrun, give up immediately. */
            if (dma_underrun)
                goto abort;
-            
-            /* Also finish if the sample session is over. */
-            if ((clock - start_time) >= f->milliseconds)
-                goto abort;
        }

        uint8_t dma_buffer_usage = 0;
@@ -399,14 +350,15 @@ static void cmd_read(struct read_frame* f)
            crunch(&cs);
            dma_buffer_usage += BUFFER_SIZE - cs.inputlen;
            count++;
-            
-            /* If there is no available space in the output buffer, flush the buffer via
-             * USB and go again. */
            if (cs.outputlen == 0)
            {
-                wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
+                while (USBFS_GetEPState(FLUXENGINE_DATA_IN_EP_NUM) != USBFS_IN_BUFFER_EMPTY)
+                {
+                    if (index_irq || dma_underrun)
+                        goto abort;
+                }
+
                USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE);
-                
                cs.outputptr = usb_buffer;
                cs.outputlen = BUFFER_SIZE;
            }
@@ -414,33 +366,22 @@ static void cmd_read(struct read_frame* f)
        dma_reading_from_td = NEXT_BUFFER(dma_reading_from_td);
    }
 abort:;
-    bool saved_dma_underrun = dma_underrun;
+    CAPTURE_CONTROL_Write(0);
    CyDmaChSetRequest(dma_channel, CY_DMA_CPU_TERM_CHAIN);
    while (CyDmaChGetRequest(dma_channel))
        ;

    donecrunch(&cs);
    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
-    /* If there's a complete packet waiting, send it. */
+    unsigned zz = cs.outputlen;
    if (cs.outputlen != BUFFER_SIZE)
-    {
-        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE);
-        wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
-    }
-    if ((cs.outputlen != 0) && (cs.outputlen != BUFFER_SIZE))
-    {
-        /* If there's a partial packet waiting, send it; this will also terminate the transfer. */
        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, usb_buffer, BUFFER_SIZE-cs.outputlen);
-    }
-    else
-    {
-        /* Otherwise just terminate the transfer. */
+    if ((cs.outputlen == BUFFER_SIZE) || (cs.outputlen == 0))
        USBFS_LoadInEP(FLUXENGINE_DATA_IN_EP_NUM, NULL, 0);
-    }
    wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
    deinit_dma();

-    if (saved_dma_underrun)
+    if (dma_underrun)
    {
        print("underrun after %d packets");
        send_error(F_ERROR_UNDERRUN);
@@ -450,7 +391,7 @@ abort:;
        DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_READ_REPLY);
        send_reply(&r);
    }
-    print("count=%d i=%d d=%d", count, index_irq, dma_underrun);
+    print("count=%d i=%d d=%d zz=%d", count, index_irq, dma_underrun, zz);
 }

 static void init_replay_dma(void)
@@ -471,28 +412,25 @@ static void init_replay_dma(void)

        CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],
            CY_DMA_TD_INC_SRC_ADR | SEQUENCER_DMA__TD_TERMOUT_EN);
-        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)REPLAY_FIFO_FIFO_PTR));
+        CyDmaTdSetAddress(td[i], LO16((uint32)&dma_buffer[i]), LO16((uint32)&SEQUENCER_DATAPATH_F0_REG));
    }    
 }

 static void cmd_write(struct write_frame* f)
 {
-    print("cmd_write");
-    
    if (f->bytes_to_write % FRAME_SIZE)
    {
        send_error(F_ERROR_INVALID_VALUE);
        return;
    }
    
-    SEQUENCER_CONTROL_Write(1); /* put the sequencer into reset */
-
    SIDE_REG_Write(f->side);
+    SEQUENCER_CONTROL_Write(1); /* reset */
    {
-        uint8_t i = CyEnterCriticalSection();        
-        REPLAY_FIFO_SET_LEVEL_NORMAL;
-        REPLAY_FIFO_CLEAR;
-        REPLAY_FIFO_SINGLE_BUFFER_UNSET;
+        uint8_t i = CyEnterCriticalSection();
+        SEQUENCER_DATAPATH_F0_SET_LEVEL_NORMAL;
+        SEQUENCER_DATAPATH_F0_CLEAR;
+        SEQUENCER_DATAPATH_F0_SINGLE_BUFFER_UNSET;
        CyExitCriticalSection(i);
    }
    seek_to(current_track);    
@@ -514,8 +452,6 @@ static void cmd_write(struct write_frame* f)
    int old_reading_from_td = -1;
    for (;;)
    {
-        CyWdtClear();
-
        /* Read data from USB into the buffers. */
        
        if (NEXT_BUFFER(dma_writing_to_td) != dma_reading_from_td)
@@ -619,7 +555,7 @@ abort:
        CyDmaChDisable(dma_channel);
    }
    
-    print("p=%d cr=%d cw=%d f=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, writing, index_irq, dma_underrun);
+    //debug("p=%d cr=%d cw=%d f=%d l=%d w=%d index=%d underrun=%d", packets, count_read, count_written, finished, listening, writing, index_irq, dma_underrun);
    if (!finished)
    {
        while (count_read < packets)
@@ -637,7 +573,6 @@ abort:
    }
    
    deinit_dma();
-    print("write finished");
    
    if (dma_underrun)
    {
@@ -672,101 +607,17 @@ static void cmd_erase(struct erase_frame* f)

 static void cmd_set_drive(struct set_drive_frame* f)
 {
-    set_drive_flags(f);
+    if (current_drive_flags != f->drive_flags)
+    {
+        current_drive_flags = f->drive_flags;
+        DRIVE_REG_Write(current_drive_flags);
+        homed = false;
+    }
    
    DECLARE_REPLY_FRAME(struct any_frame, F_FRAME_SET_DRIVE_REPLY);
    send_reply((struct any_frame*) &r);
 }
-
-static uint16_t read_output_voltage_mv(void)
-{
-    OUTPUT_VOLTAGE_ADC_StartConvert();
-    OUTPUT_VOLTAGE_ADC_IsEndConversion(OUTPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
-    uint16_t samples = OUTPUT_VOLTAGE_ADC_GetResult16();
-    return OUTPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
-}
-
-static void read_output_voltages(struct voltages* v)
-{
-    SIDE_REG_Write(1); /* set DIR to low (remember this is inverted) */
-    CyDelay(100);
-    v->logic0_mv = read_output_voltage_mv();
-
-    SIDE_REG_Write(0);
-    CyDelay(100);
-    v->logic1_mv = read_output_voltage_mv();
-}
-
-static uint16_t read_input_voltage_mv(void)
-{
-    INPUT_VOLTAGE_ADC_StartConvert();
-    INPUT_VOLTAGE_ADC_IsEndConversion(INPUT_VOLTAGE_ADC_WAIT_FOR_RESULT);
-    uint16_t samples = INPUT_VOLTAGE_ADC_GetResult16();
-    return INPUT_VOLTAGE_ADC_CountsTo_mVolts(samples);
-}
-
-static void read_input_voltages(struct voltages* v)
-{
-    home();
-    CyDelay(50);
-    v->logic0_mv = read_input_voltage_mv();
-    
-    step(STEP_AWAYFROM0);
-    CyDelay(50);
-    v->logic1_mv = read_input_voltage_mv();
-}
-
-static void cmd_measure_voltages(void)
-{
-    stop_motor();
-    INPUT_VOLTAGE_ADC_Start();
-    INPUT_VOLTAGE_ADC_SetPower(INPUT_VOLTAGE_ADC__HIGHPOWER);
-    OUTPUT_VOLTAGE_ADC_Start();
-    OUTPUT_VOLTAGE_ADC_SetPower(OUTPUT_VOLTAGE_ADC__HIGHPOWER);
-    
-    DECLARE_REPLY_FRAME(struct voltages_frame, F_FRAME_MEASURE_VOLTAGES_REPLY);
-    
-    CyWdtClear();
-    MOTOR_REG_Write(0); /* should be ignored anyway */
-    DRIVESELECT_REG_Write(0); /* deselect both drives */
-    CyDelay(200); /* wait for things to settle */
-    read_output_voltages(&r.output_both_off);
-    read_input_voltages(&r.input_both_off);
-
-    CyWdtClear();
-    DRIVESELECT_REG_Write(1); /* select drive 0 */
-    CyDelay(50);
-    read_output_voltages(&r.output_drive_0_selected);
-    read_input_voltages(&r.input_drive_0_selected);
-    MOTOR_REG_Write(1);
-    CyDelay(300);
-    CyWdtClear();
-    read_output_voltages(&r.output_drive_0_running);
-    read_input_voltages(&r.input_drive_0_running);
-    MOTOR_REG_Write(0);
-    CyDelay(300);
-    
-    CyWdtClear();
-    DRIVESELECT_REG_Write(2); /* select drive 1 */
-    CyDelay(50);
-    read_output_voltages(&r.output_drive_1_selected);
-    read_input_voltages(&r.input_drive_1_selected);
-    MOTOR_REG_Write(1);
-    CyDelay(300);
-    CyWdtClear();
-    read_output_voltages(&r.output_drive_1_running);
-    read_input_voltages(&r.input_drive_1_running);
-    MOTOR_REG_Write(0);
-    CyDelay(300);
-
-    CyWdtClear();
-    DRIVESELECT_REG_Write(0);
-    homed = false;
-    INPUT_VOLTAGE_ADC_Stop();
-    OUTPUT_VOLTAGE_ADC_Stop();
-    send_reply((struct any_frame*) &r);
-}
-
+   
 static void handle_command(void)
 {
    static uint8_t input_buffer[FRAME_SIZE];
@@ -811,10 +662,6 @@ static void handle_command(void)
        case F_FRAME_SET_DRIVE_CMD:
            cmd_set_drive((struct set_drive_frame*) f);
            break;
-        
-        case F_FRAME_MEASURE_VOLTAGES_CMD:
-            cmd_measure_voltages();
-            break;
            
        default:
            send_error(F_ERROR_BAD_COMMAND);
@@ -827,11 +674,9 @@ int main(void)
    CySysTickStart();
    CySysTickSetCallback(4, system_timer_cb);
    INDEX_IRQ_StartEx(&index_irq_cb);
-    SAMPLER_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
+    CAPTURE_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
    SEQUENCER_DMA_FINISHED_IRQ_StartEx(&replay_dma_finished_irq_cb);
-    INPUT_VOLTAGE_ADC_Stop();
-    OUTPUT_VOLTAGE_ADC_Stop();
-    DRIVESELECT_REG_Write(0);
+    DRIVE_REG_Write(0);
    UART_Start();
    USBFS_Start(0, USBFS_DWR_VDDD_OPERATION);
    
@@ -847,7 +692,10 @@ int main(void)
        {
            uint32_t time_on = clock - motor_on_time;
            if (time_on > MOTOR_ON_TIME)
-                stop_motor();
+            {
+                MOTOR_REG_Write(0);
+                motor_on = false;
+            }
        }
        
        if (!USBFS_GetConfiguration() || USBFS_IsConfigurationChanged())
@@ -861,7 +709,6 @@ int main(void)
        
        if (USBFS_GetEPState(FLUXENGINE_CMD_OUT_EP_NUM) == USBFS_OUT_BUFFER_FULL)
        {
-            set_drive_flags(&current_drive_flags);
            handle_command();
            USBFS_EnableOutEP(FLUXENGINE_CMD_OUT_EP_NUM);
            print("idle");
--- a/18
+++ b/18
@@ -1,13 +1,8 @@
 PACKAGES = zlib sqlite3 libusb-1.0

-export CFLAGS = --std=c++14 -ffunction-sections -fdata-sections
-export LDFLAGS =
-
-export COPTFLAGS = -Os
-export LDOPTFLAGS = -Os -s
-
-export CDBGFLAGS = -O0 -g
-export LDDBGFLAGS = -O0 -g
+export CFLAGS = -Os -g --std=c++14 \
+	-ffunction-sections -fdata-sections
+export LDFLAGS = -Os

 ifeq ($(OS), Windows_NT)
 export CXX = /mingw32/bin/g++
@@ -18,13 +13,6 @@ export LDFLAGS +=
 export LIBS = -static -lz -lsqlite3 -lusb-1.0
 export EXTENSION = .exe
 else
-
-packages-exist = $(shell pkg-config --exists $(PACKAGES) && echo yes)
-ifneq ($(packages-exist),yes)
-$(warning These pkg-config packages are installed: $(shell pkg-config --list-all | sort | awk '{print $$1}'))
-$(error You must have these pkg-config packages installed: $(PACKAGES))
-endif
-
 export CXX = g++
 export AR = ar rcs
 export STRIP = strip
--- a/README.md
+++ b/README.md
@@ -89,7 +89,7 @@ people who've had it work).
 | [Brother 120kB](doc/disk-brother.md)     |  🦄   |        |                                     |
 | [Brother 240kB](doc/disk-brother.md)     |  🦄   |   🦄   |                                     |
 | [Brother FB-100](doc/disk-fb100.md)      |  🦖   |        | Tandy Model 100, Husky Hunter, knitting machines |
-| [Macintosh 800kB](doc/disk-macintosh.md) |  🦖   |        | and probably the 400kB too          |
+| [Macintosh 800kB](doc/disk-macintosh.md) |  🦄   |        | and probably the 400kB too          |
 | [TRS-80](doc/disk-trs80.md)              |  🦖   |        | a minor variation of the IBM scheme |
 {: .datatable }

--- a/arch/amiga/amiga.cc
+++ b/arch/amiga/amiga.cc
@@ -1,101 +0,0 @@
-#include "globals.h"
-#include "record.h"
-#include "decoders/decoders.h"
-#include "amiga.h"
-#include "bytes.h"
-#include "fmt/format.h"
-
-uint32_t amigaChecksum(const Bytes& bytes)
-{
-    ByteReader br(bytes);
-    uint32_t checksum = 0;
-
-    assert((bytes.size() & 3) == 0);
-    while (!br.eof())
-        checksum ^= br.read_be32();
-
-    return checksum & 0x55555555;
-}
-
-static uint8_t everyother(uint16_t x)
-{
-	                  /* aabb ccdd eeff gghh */
-	x &= 0x6666;      /* 0ab0 0cd0 0ef0 0gh0 */
-	x >>= 1;          /* 00ab 00cd 00ef 00gh */
-	x |= x << 2;      /* abab cdcd efef ghgh */
-	x &= 0x3c3c;      /* 00ab cd00 00ef gh00 */
-	x >>= 2;          /* 0000 abcd 0000 efgh */
-	x |= x >> 4;      /* 0000 abcd abcd efgh */
-	return x;
-}
-
-Bytes amigaInterleave(const Bytes& input)
-{
-	Bytes output;
-	ByteWriter bw(output);
-
-	/* Write all odd bits. (Numbering starts at 0...) */
-
-	{
-		ByteReader br(input);
-		while (!br.eof())
-		{
-			uint16_t x = br.read_be16();
-			x &= 0xaaaa;       /* a0b0 c0d0 e0f0 g0h0 */
-			x |= x >> 1;       /* aabb ccdd eeff gghh */
-			x = everyother(x); /* 0000 0000 abcd efgh */
-			bw.write_8(x);
-		}
-	}
-
-	/* Write all even bits. */
-
-	{
-		ByteReader br(input);
-		while (!br.eof())
-		{
-			uint16_t x = br.read_be16();
-			x &= 0x5555;       /* 0a0b 0c0d 0e0f 0g0h */
-			x |= x << 1;       /* aabb ccdd eeff gghh */
-			x = everyother(x); /* 0000 0000 abcd efgh */
-			bw.write_8(x);
-		}
-	}
-
-	return output;
-}
-
-Bytes amigaDeinterleave(const uint8_t*& input, size_t len)
-{
-    assert(!(len & 1));
-    const uint8_t* odds = &input[0];
-    const uint8_t* evens = &input[len/2];
-    Bytes output;
-    ByteWriter bw(output);
-
-    for (size_t i=0; i<len/2; i++)
-    {
-        uint8_t o = *odds++;
-        uint8_t e = *evens++;
-
-        /* This is the 'Interleave bits with 64-bit multiply' technique from
-         * http://graphics.stanford.edu/~seander/bithacks.html#InterleaveBMN
-         */
-        uint16_t result =
-            (((e * 0x0101010101010101ULL & 0x8040201008040201ULL)
-                * 0x0102040810204081ULL >> 49) & 0x5555) |
-            (((o * 0x0101010101010101ULL & 0x8040201008040201ULL)
-                * 0x0102040810204081ULL >> 48) & 0xAAAA);
-        
-        bw.write_be16(result);
-    }
-
-    input += len;
-    return output;
-}
-
-Bytes amigaDeinterleave(const Bytes& input)
-{
-	const uint8_t* ptr = input.cbegin();
-	return amigaDeinterleave(ptr, input.size());
-}
--- a/arch/amiga/amiga.h
+++ b/arch/amiga/amiga.h
@@ -1,17 +1,12 @@
 #ifndef AMIGA_H
 #define AMIGA_H

-#include "encoders/encoders.h"
-
 #define AMIGA_SECTOR_RECORD 0xaaaa44894489LL

-#define AMIGA_TRACKS_PER_DISK 80
-#define AMIGA_SECTORS_PER_TRACK 11
 #define AMIGA_RECORD_SIZE 0x21f

 class Sector;
 class Fluxmap;
-class SectorSet;

 class AmigaDecoder : public AbstractDecoder
 {
@@ -22,20 +17,4 @@ public:
    void decodeSectorRecord();
 };

-class AmigaEncoder : public AbstractEncoder
-{
-public:
-	virtual ~AmigaEncoder() {}
-
-public:
-    std::unique_ptr<Fluxmap> encode(int physicalTrack, int physicalSide, const SectorSet& allSectors);
-};
-
-extern FlagGroup amigaEncoderFlags;
-
-extern uint32_t amigaChecksum(const Bytes& bytes);
-extern Bytes amigaInterleave(const Bytes& input);
-extern Bytes amigaDeinterleave(const uint8_t*& input, size_t len);
-extern Bytes amigaDeinterleave(const Bytes& input);
-
 #endif
--- a/arch/amiga/decoder.cc
+++ b/arch/amiga/decoder.cc
@@ -21,6 +21,47 @@
         
 static const FluxPattern SECTOR_PATTERN(48, AMIGA_SECTOR_RECORD);

+static Bytes deinterleave(const uint8_t*& input, size_t len)
+{
+    assert(!(len & 1));
+    const uint8_t* odds = &input[0];
+    const uint8_t* evens = &input[len/2];
+    Bytes output;
+    ByteWriter bw(output);
+
+    for (size_t i=0; i<len/2; i++)
+    {
+        uint8_t o = *odds++;
+        uint8_t e = *evens++;
+
+        /* This is the 'Interleave bits with 64-bit multiply' technique from
+         * http://graphics.stanford.edu/~seander/bithacks.html#InterleaveBMN
+         */
+        uint16_t result =
+            (((e * 0x0101010101010101ULL & 0x8040201008040201ULL)
+                * 0x0102040810204081ULL >> 49) & 0x5555) |
+            (((o * 0x0101010101010101ULL & 0x8040201008040201ULL)
+                * 0x0102040810204081ULL >> 48) & 0xAAAA);
+        
+        bw.write_be16(result);
+    }
+
+    input += len;
+    return output;
+}
+
+static uint32_t checksum(const Bytes& bytes)
+{
+    ByteReader br(bytes);
+    uint32_t checksum = 0;
+
+    assert((bytes.size() & 3) == 0);
+    while (!br.eof())
+        checksum ^= br.read_be32();
+
+    return checksum & 0x55555555;
+}
+
 AbstractDecoder::RecordType AmigaDecoder::advanceToNextRecord()
 {
    _sector->clock = _fmr->seekToPattern(SECTOR_PATTERN);
@@ -37,22 +78,22 @@ void AmigaDecoder::decodeSectorRecord()

    const uint8_t* ptr = bytes.begin() + 3;

-    Bytes header = amigaDeinterleave(ptr, 4);
-    Bytes recoveryinfo = amigaDeinterleave(ptr, 16);
+    Bytes header = deinterleave(ptr, 4);
+    Bytes recoveryinfo = deinterleave(ptr, 16);

    _sector->logicalTrack = header[1] >> 1;
    _sector->logicalSide = header[1] & 1;
    _sector->logicalSector = header[2];

-    uint32_t wantedheaderchecksum = amigaDeinterleave(ptr, 4).reader().read_be32();
-    uint32_t gotheaderchecksum = amigaChecksum(rawbytes.slice(6, 40));
+    uint32_t wantedheaderchecksum = deinterleave(ptr, 4).reader().read_be32();
+    uint32_t gotheaderchecksum = checksum(rawbytes.slice(6, 40));
    if (gotheaderchecksum != wantedheaderchecksum)
        return;

-    uint32_t wanteddatachecksum = amigaDeinterleave(ptr, 4).reader().read_be32();
-    uint32_t gotdatachecksum = amigaChecksum(rawbytes.slice(62, 1024));
+    uint32_t wanteddatachecksum = deinterleave(ptr, 4).reader().read_be32();
+    uint32_t gotdatachecksum = checksum(rawbytes.slice(62, 1024));

    _sector->data.clear();
-    _sector->data.writer().append(amigaDeinterleave(ptr, 512)).append(recoveryinfo);
+    _sector->data.writer().append(deinterleave(ptr, 512)).append(recoveryinfo);
    _sector->status = (gotdatachecksum == wanteddatachecksum) ? Sector::OK : Sector::BAD_CHECKSUM;
 }
--- a/arch/amiga/encoder.cc
+++ b/arch/amiga/encoder.cc
@@ -1,126 +0,0 @@
-#include "globals.h"
-#include "record.h"
-#include "decoders/decoders.h"
-#include "encoders/encoders.h"
-#include "amiga.h"
-#include "crc.h"
-#include "sectorset.h"
-#include "writer.h"
-
-FlagGroup amigaEncoderFlags;
-
-static DoubleFlag clockRateUs(
-	{ "--clock-rate" },
-	"Encoded data clock rate (microseconds).",
-	2.00);
-
-static DoubleFlag postIndexGapMs(
-	{ "--post-index-gap" },
-	"Post-index gap before first sector header (milliseconds).",
-	0.5);
-
-static int charToInt(char c)
-{
-	if (isdigit(c))
-		return c - '0';
-	return 10 + tolower(c) - 'a';
-}
-
-static void write_bits(std::vector<bool>& bits, unsigned& cursor, const std::vector<bool>& src)
-{
-	for (bool bit : src)
-	{
-		if (cursor < bits.size())
-			bits[cursor++] = bit;
-	}
-}
-
-static void write_bits(std::vector<bool>& bits, unsigned& cursor, uint64_t data, int width)
-{
-	cursor += width;
-	for (int i=0; i<width; i++)
-	{
-		unsigned pos = cursor - i - 1;
-		if (pos < bits.size())
-			bits[pos] = data & 1;
-		data >>= 1;
-	}
-}
-
-static void write_interleaved_bytes(std::vector<bool>& bits, unsigned& cursor, const Bytes& bytes)
-{
-	assert(!(bytes.size() & 3));
-	Bytes interleaved = amigaInterleave(bytes);
-	encodeMfm(bits, cursor, interleaved);
-}
-
-static void write_interleaved_bytes(std::vector<bool>& bits, unsigned& cursor, uint32_t data)
-{
-	Bytes b(4);
-	ByteWriter bw(b);
-	bw.write_be32(data);
-	write_interleaved_bytes(bits, cursor, b);
-}
-
-static void write_sector(std::vector<bool>& bits, unsigned& cursor, const Sector* sector)
-{
-	if ((sector->data.size() != 512) && (sector->data.size() != 528))
-		Error() << "unsupported sector size --- you must pick 512 or 528";
-
-    write_bits(bits, cursor, AMIGA_SECTOR_RECORD, 6*8);
-
-	std::vector<bool> headerBits(20*16);
-	unsigned headerCursor = 0;
-
-	Bytes header = 
-		{
-			0xff, /* Amiga 1.0 format byte */
-			(uint8_t) ((sector->logicalTrack<<1) | sector->logicalSide),
-			(uint8_t) sector->logicalSector,
-			(uint8_t) (AMIGA_SECTORS_PER_TRACK - sector->logicalSector)
-		};
-	write_interleaved_bytes(headerBits, headerCursor, header);
-	Bytes recoveryInfo(16);
-	if (sector->data.size() == 528)
-		recoveryInfo = sector->data.slice(512, 16);
-	write_interleaved_bytes(headerBits, headerCursor, recoveryInfo);
-
-	std::vector<bool> dataBits(512*16);
-	unsigned dataCursor = 0;
-	write_interleaved_bytes(dataBits, dataCursor, sector->data);
-
-	write_bits(bits, cursor, headerBits);
-	uint32_t headerChecksum = amigaChecksum(toBytes(headerBits));
-	write_interleaved_bytes(bits, cursor, headerChecksum);
-	uint32_t dataChecksum = amigaChecksum(toBytes(dataBits));
-	write_interleaved_bytes(bits, cursor, dataChecksum);
-	write_bits(bits, cursor, dataBits);
-}
-
-std::unique_ptr<Fluxmap> AmigaEncoder::encode(
-	int physicalTrack, int physicalSide, const SectorSet& allSectors)
-{
-	if ((physicalTrack < 0) || (physicalTrack >= AMIGA_TRACKS_PER_DISK))
-		return std::unique_ptr<Fluxmap>();
-
-	int bitsPerRevolution = 200000.0 / clockRateUs;
-	std::vector<bool> bits(bitsPerRevolution);
-	unsigned cursor = 0;
-
-    fillBitmapTo(bits, cursor, postIndexGapMs * 1000 / clockRateUs, { true, false });
-
-	for (int sectorId=0; sectorId<AMIGA_SECTORS_PER_TRACK; sectorId++)
-	{
-		const auto& sectorData = allSectors.get(physicalTrack, physicalSide, sectorId);
-		write_sector(bits, cursor, sectorData);
-    }
-
-	if (cursor >= bits.size())
-		Error() << "track data overrun";
-	fillBitmapTo(bits, cursor, bits.size(), { true, false });
-
-	std::unique_ptr<Fluxmap> fluxmap(new Fluxmap);
-	fluxmap->appendBits(bits, clockRateUs*1e3);
-	return fluxmap;
-}
-
--- a/arch/brother/encoder.cc
+++ b/arch/brother/encoder.cc
@@ -154,7 +154,7 @@ std::unique_ptr<Fluxmap> BrotherEncoder::encode(
 		write_sector_data(bits, cursor, sectorData->data);
 	}

-	if (cursor >= bits.size())
+	if (cursor > bits.size())
 		Error() << "track data overrun";
 	fillBitmapTo(bits, cursor, bits.size(), { true, false });

--- a/arch/ibm/decoder.cc
+++ b/arch/ibm/decoder.cc
@@ -73,10 +73,8 @@ const FluxPattern FM_TRS80DAM2_PATTERN(16, 0xf56c);
 * encoding (you can't do 10 00). So this can't be spoofed by user data.
 * 
 * shifted: 10 00 10 01 00 01 00 1
- * 
- * It's repeated three times.
 */
-const FluxPattern MFM_PATTERN(48, 0x448944894489LL);
+const FluxPattern MFM_PATTERN(16, 0x4489);

 const FluxMatchers ANY_RECORD_PATTERN(
    {
@@ -102,8 +100,7 @@ AbstractDecoder::RecordType IbmDecoder::advanceToNextRecord()
    if (_currentHeaderLength > 0)
        readRawBits(_currentHeaderLength*16);
    auto idbits = readRawBits(16);
-    const Bytes idbytes = decodeFmMfm(idbits);
-    uint8_t id = idbytes.slice(0, 1)[0];
+    uint8_t id = decodeFmMfm(idbits).slice(0, 1)[0];
    seek(here);
    
    switch (id)
--- a/doc/Index_sensor_mod_FDD_1.1.pdf
+++ b/doc/Index_sensor_mod_FDD_1.1.pdf
--- a/doc/building.md
+++ b/doc/building.md
@@ -182,7 +182,7 @@ install some support packages.

  - For Linux (this is Ubuntu, but this should apply to Debian too):
  `ninja-build`, `libusb-1.0-0-dev`, `libsqlite3-dev`.
-  - For OSX with Homebrew: `ninja`, `libusb`, `pkg-config`, `sqlite`.
+  - For OSX with Homebrew: `ninja`.
  - For Windows with MSYS2: `make`, `ninja`, `mingw-w64-i686-libusb`,
  `mingw-w64-i686-sqlite3`, `mingw-w64-i686-zlib`, `mingw-w64-i686-gcc`.

--- a/doc/disk-amiga.md
+++ b/doc/disk-amiga.md
@@ -10,7 +10,7 @@ Bizarrely, the data in each sector is stored with all the odd bits first, and
 then all the even bits. This is tied into the checksum algorithm, which is
 distinctly subpar and not particularly good at detecting errors.

-Reading disks
+Reading discs
 -------------

 Just do:
@@ -34,28 +34,6 @@ You will end up with a 929280 byte long image which you probably _can't_ use
 in an emulator; each sector will contain the 512 bytes of user payload
 followed by the 16 bytes of metadata.

-Writing disks
-------------
-
-Just do:
-
-```
-fluxengine write amiga -i amiga.adf
-```
-
-This will rake a normal 901120 byte long ADF file and write it to a DD disk.
-Note that writing to an HD disk will probably not work (this will depend on
-your drive and disk and potential FluxEngine bugs I'm still working on ---
-please [get in touch](https://github.com/davidgiven/fluxengine/issues/new) if
-you have any insight here).
-
-If you want to write the metadata as well, specify a 528 byte sector size for
-the output image and supply a 929280 byte long file as described above.
-
-```
-fluxengine write amiga -i amiga.adf:b=528
-```
-
 Useful references
 -----------------

--- a/doc/disk-brother.md
+++ b/doc/disk-brother.md
@@ -129,8 +129,8 @@ reverse engineered it to find out.

 Standard Linux mtools will access the filesystem image and allow you to move
 files in and out. However, you'll need to change the media type bytes at
-offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. The
-supplied `brother240tool` will do this. Once done, this will work:
+offsets 0x015 and 0x100 from 0x58 to 0xf0 before mtools will touch it. Once
+done, this will work:

 ```
 mdir -i brother.img
--- a/doc/disk-macintosh.md
+++ b/doc/disk-macintosh.md
@@ -28,16 +28,8 @@ for example the Commodore 64 1541 drive, changed bitrate this way.
 But Macintosh disks used a constant bitrate and changed the speed that the
 disk spun instead to achieve the same effect...

-_Anyway_: FluxEngine will read them fine on conventional drives.
-Because it's clever.
-
-**Big note.** Apparently --- and I'm still getting to the bottom of this ---
-some drives work and some don't. My drives produce about 90% good reads of
-known good disks. One rumour I've heard is that drives sometimes include
-filters which damage the signals at very particular intervals which Mac disks
-use, but frankly this seems unlikely; it could be a software issue at my end
-and I'm investigating. If you have any insight, please [get in
-touch](https://github.com/davidgiven/fluxengine/issues/new).
+_Anyway_: FluxEngine will read them fine on a conventional drive. Because
+it's clever.

 Reading discs
 -------------
--- a/doc/faq.md
+++ b/doc/faq.md
@@ -48,7 +48,7 @@ haven't had the chance to try it end-for-end. I really need a hard-sectored

 **Q.** Does it work with flippy disks?

-Uhhh... maybe?
+Uhhh... probably not.

 So the problem with flippy disks (5.25" single-sided disks which could be
 inserted upside down to read the second side) is the index hole. Trouble is,
@@ -79,26 +79,16 @@ the other. But a flippy disk has both sets of tracks in the same place,
 because they're both accessed using the side 0 head...

 The only real way round this is to modify a 5.25" drive. That's _seriously_
-not in FluxEngine's remit, but I've had some [excellent documentation
-contributed](Index_sensor_mod_FDD_1.1.pdf) on how to do this. I've never done
-it myself; if you try this and it works/doesn't work, as always, [get in
-touch](https://github.com/davidgiven/fluxengine/issues/new).
+not in FluxEngine's remit. Sorry.

-Another option is to fake the index signal to the drive completely. The
-FluxEngine emits suitable pulses for a 300RPM drive on pin 3[0] and the
-equivalent pulses for a 360RPM drive on pin 3[1]. Disclaimer: I have never used
-these.
-
-**Q.** Is this like Supercard Pro / KryoFlux / Catweasel / DiskFerret? Do you
-*support KryoFlux
+**Q.** Is this like KryoFlux / Catweasel / DiskFerret? Do you support KryoFlux
 stream files?

 **A.** It's very like all of these; the idea's old, and lots of people have
 tried it (you can get away with any sufficiently fast microcontroller and
 enough RAM). FluxEngine can read from KryoFlux stream files natively, and
-there's a tool which will let you convert at least one kind of Catweasel
-files and Supercard Pro files to and from FluxEngine's native flux file
-format.
+there's a tool which will let you convert at least one kind of Catweasel file
+to FluxEngine's native flux file format.

 **Q.** Can I use this to make exact copies of disks?

--- a/doc/technical.md
+++ b/doc/technical.md
@@ -123,12 +123,8 @@ admittedly expensive.)
    sheet](http://www.bitsavers.org/pdf/mitsubishi/floppy/M4851/TJ2-G30211A_M4851_DSHH_48TPI_OEM_Manual_Nov83.pdf):
    the equivalent data sheet for a representative 5.25" drive.

-  - [The DRG Business Machines YD-174 manual](https://electrickery.hosting.philpem.me.uk/comp/divcomp/doc/YE_Data_YD-174_8inchFloppyDriveTechnicalManual.pdf):
-	the equivalent manual (data sheets hadn't been invented then) for a
-	representative 8" drive.
-
  - [KryoFlux stream file
    documentation](https://www.kryoflux.com/download/kryoflux_stream_protocol_rev1.1.pdf):
    the format of KryoFlux stream files (partially supported by FluxEngine)

-  
+  
--- a/doc/using.md
+++ b/doc/using.md
@@ -51,7 +51,7 @@ In order to do anything useful, you have to plug it in to a floppy disk drive (o
     rpm for a 3.5" disk, or 360 rpm for a 5.25" disk. If it doesn't, please
     [get in touch](https://github.com/davidgiven/fluxengine/issues/new).

-  7. Do `fluxengine test bulktransport` from the shell. It'll measure your USB
+  7. Do `fluxengine testbulktransport` from the shell. It'll measure your USB
     bandwidth. Ideally you should be getting above 900kB/s. FluxEngine needs
     about 850kB/s, so if you're getting less than this, try a different USB
     port.
@@ -64,16 +64,6 @@ In order to do anything useful, you have to plug it in to a floppy disk drive (o

  9. Profit!

-## Bonus hardware features
-
-For advanced users, the board has a few extra signals which are useful for special purposes.
-
-  - Pin 3[0] produces short pulses every 200ms. This is useful for spoofing
-    index signals to 300 RPM drives; for example, to read flippy disks.
-
-  - Pin 3[1] is the same, but produces the pulses every 166ms; this works with
-    360 RPM drives.
-
 ## The programs

 I'm sorry to say that the client program is very badly documented --- it's
@@ -186,23 +176,6 @@ case, and reading the disk label is much more reliable.
 [Lots more information on high density vs double density disks can be found
 here.](http://www.retrotechnology.com/herbs_stuff/guzis.html)

-### Other important flags
-
-These flags apply to many operations and are useful for modifying the overall
-behaviour.
-
-  - `--revolutions=X`: when reading, spin the disk X times. Many formats
-  require `--revolutions=2` (which should happen automatically); or you can
-  increase the number to sample more data.
-
-  - `--index-source=X`, `--write-index-source=X`: set the source of index
-  pulses when reading or writing respectively. This is for use with drives
-  which don't produce index pulse data. Use 0 to get index pulses from the
-  drive, 1 to fake 300RPM pulses, or 2 to fake 360RPM pulses. Note this has
-  no effect on the _drive_, so it doesn't help with flippy disks, but is
-  useful for using very old drives with FluxEngine itself. If you use this
-  option, then any index marks in the sampled flux are, of course, garbage.
-
 ### The commands

 The FluxEngine client software is a largely undocumented set of small tools.
@@ -216,13 +189,12 @@ directory.
  - `fluxengine inspect`: dumps the raw pulsetrain / bitstream to stdout.
  Mainly useful for debugging.

-  - `fluxengine read *`: reads various formats of disk. See the per-format
+  - `fluxengine read*`: reads various formats of disk. See the per-format
  documentation linked from the table above. These all take an optional
  `--write-flux` option which will cause the raw flux to be written to the
-  specified file. There are various `--dump` options for showing raw data
-  during the decode process.
+  specified file.

-  - `fluxengine write *`: writes various formats of disk. Again, see the
+  - `fluxengine write*`: writes various formats of disk. Again, see the
  per-format documentation above.

  - `fluxengine writeflux`: writes raw flux files. This is much less useful
@@ -241,13 +213,10 @@ directory.
  - `fluxengine seek`: moves the head. Mainly useful for finding out whether
  your drive can seek to track 82. (Mine can't.)

-  - `fluxengine test bulktransport`: measures your USB throughput. You need
+  - `fluxengine testbulktransport`: measures your USB throughput. You need
  about 600kB/s for FluxEngine to work. You don't need a disk in the drive
  for this one.

-  - `fluxengine test voltages`: measures your FDD bus signal voltages, which
-  is useful for testing for termination issues.
-
  - `fluxengine upgradefluxfile`: occasionally I need to upgrade the flux
  file format in a non-backwards-compatible way; this tool will upgrade flux
  files to the new format.
--- a/lib/decoders/decoders.cc
+++ b/lib/decoders/decoders.cc
@@ -25,7 +25,7 @@ void AbstractDecoder::decodeToSectors(Track& track)
    beginTrack();
    for (;;)
    {
-        Fluxmap::Position recordStart = fmr.tell();
+        Fluxmap::Position recordStart = sector.position = fmr.tell();
        sector.clock = 0;
        sector.status = Sector::MISSING;
        sector.data.clear();
@@ -41,7 +41,7 @@ void AbstractDecoder::decodeToSectors(Track& track)

        /* Read the sector record. */

-        sector.position = recordStart = fmr.tell();
+        recordStart = fmr.tell();
        decodeSectorRecord();
        Fluxmap::Position recordEnd = fmr.tell();
        pushRecord(recordStart, recordEnd);
@@ -51,19 +51,14 @@ void AbstractDecoder::decodeToSectors(Track& track)

            sector.headerStartTime = recordStart.ns();
            sector.headerEndTime = recordEnd.ns();
-			for (;;)
-			{
-				r = advanceToNextRecord();
-				if (r != UNKNOWN_RECORD)
-					break;
-				if (fmr.readNextMatchingOpcode(F_OP_PULSE) == 0)
-                    break;
-			}
-            recordStart = fmr.tell();
+            r = advanceToNextRecord();
            if (r == DATA_RECORD)
+            {
+                recordStart = fmr.tell();
                decodeDataRecord();
-            recordEnd = fmr.tell();
-            pushRecord(recordStart, recordEnd);
+                recordEnd = fmr.tell();
+                pushRecord(recordStart, recordEnd);
+            }
        }
        sector.dataStartTime = recordStart.ns();
        sector.dataEndTime = recordEnd.ns();
--- a/lib/decoders/decoders.h
+++ b/lib/decoders/decoders.h
@@ -20,7 +20,6 @@ extern void setDecoderManualClockRate(double clockrate_us);

 extern Bytes decodeFmMfm(std::vector<bool>::const_iterator start,
    std::vector<bool>::const_iterator end);
-extern void encodeMfm(std::vector<bool>& bits, unsigned& cursor, const Bytes& input);

 static inline Bytes decodeFmMfm(const std::vector<bool> bits)
 { return decodeFmMfm(bits.begin(), bits.end()); }
--- a/lib/decoders/fluxmapreader.cc
+++ b/lib/decoders/fluxmapreader.cc
@@ -18,18 +18,13 @@ DoubleFlag pulseDebounceThreshold(
 static DoubleFlag clockDecodeThreshold(
    { "--bit-error-threshold" },
    "Amount of error to tolerate in pulse timing, in fractions of a clock.",
-    0.40);
+    0.20);

 static DoubleFlag clockIntervalBias(
    { "--clock-interval-bias" },
    "Adjust intervals between pulses by this many clocks before decoding.",
    -0.02);

-static DoubleFlag minimumClockUs(
-    { "--minimum-clock-us" },
-    "Refuse to detect clocks shorter than this, to avoid false positives.",
-    0.75);
-
 int FluxmapReader::readOpcode(unsigned& ticks)
 {
    ticks = 0;
@@ -227,9 +222,7 @@ nanoseconds_t FluxmapReader::seekToPattern(const FluxMatcher& pattern, const Flu
            seek(positions[intervalCount-match.intervals]);
            _pos.zeroes = match.zeroes;
            matching = match.matcher;
-            nanoseconds_t detectedClock = match.clock * NS_PER_TICK;
-            if (detectedClock > (minimumClockUs*1000))
-                return match.clock * NS_PER_TICK;
+            return match.clock * NS_PER_TICK;
        }

        for (unsigned i=0; i<intervalCount; i++)
--- a/lib/decoders/fmmfm.cc
+++ b/lib/decoders/fmmfm.cc
@@ -51,25 +51,3 @@ Bytes decodeFmMfm(

    return bytes;
 }
-
-void encodeMfm(std::vector<bool>& bits, unsigned& cursor, const Bytes& input)
-{
-    bool lastBit = false;
-    unsigned len = bits.size()-1;
-
-    for (uint8_t b : input)
-    {
-        for (int i=0; i<8; i++)
-        {
-            bool bit = b & 0x80;
-            b <<= 1;
-
-            if (cursor >= len)
-                return;
-            
-            bits[cursor++] = !lastBit && !bit;
-            bits[cursor++] = bit;
-            lastBit = bit;
-        }
-    }
-}
--- a/lib/flags.cc
+++ b/lib/flags.cc
@@ -157,8 +157,6 @@ Flag::Flag(const std::vector<std::string>& names, const std::string helptext):
    _names(names),
    _helptext(helptext)
 {
-    if (!currentFlagGroup)
-        Error() << "no flag group defined for " << *names.begin();
    _group.addFlag(this);
 }

--- a/lib/fluxsink/fluxsink.h
+++ b/lib/fluxsink/fluxsink.h
@@ -1,10 +1,6 @@
 #ifndef FLUXSINK_H
 #define FLUXSINK_H

-#include "flags.h"
-
-extern FlagGroup hardwareFluxSinkFlags;
-
 class Fluxmap;
 class FluxSpec;

--- a/lib/fluxsink/hardwarefluxsink.cc
+++ b/lib/fluxsink/hardwarefluxsink.cc
@@ -4,15 +4,8 @@
 #include "usb.h"
 #include "fluxsink/fluxsink.h"

-FlagGroup hardwareFluxSinkFlags;
-
 static bool high_density = false;

-static IntFlag indexMode(
-    { "--write-index-mode" },
-    "index pulse source (0=drive, 1=300 RPM fake source, 2=360 RPM fake source",
-    0);
-
 void setHardwareFluxSinkDensity(bool high_density)
 {
 	::high_density = high_density;
@@ -33,7 +26,7 @@ public:
 public:
    void writeFlux(int track, int side, Fluxmap& fluxmap)
    {
-        usbSetDrive(_drive, high_density, indexMode);
+        usbSetDrive(_drive, high_density);
        usbSeek(track);

        Bytes crunched = fluxmap.rawBytes().crunch();
--- a/lib/fluxsource/fluxsource.h
+++ b/lib/fluxsource/fluxsource.h
@@ -27,9 +27,8 @@ public:
    virtual bool retryable() { return false; }
 };

-extern void setHardwareFluxSourceRevolutions(double revolutions);
+extern void setHardwareFluxSourceRevolutions(int revolutions);
 extern void setHardwareFluxSourceDensity(bool high_density);
-extern void setHardwareFluxSourceSynced(bool synced);

 #endif

--- a/lib/fluxsource/hardwarefluxsource.cc
+++ b/lib/fluxsource/hardwarefluxsource.cc
@@ -3,24 +3,13 @@
 #include "fluxmap.h"
 #include "usb.h"
 #include "fluxsource/fluxsource.h"
-#include "fmt/format.h"

 FlagGroup hardwareFluxSourceFlags;

-static DoubleFlag revolutions(
+static IntFlag revolutions(
    { "--revolutions" },
    "read this many revolutions of the disk",
-    1.25);
-
-static BoolFlag synced(
-    { "--sync-with-index" },
-    "whether to wait for an index pulse before started to read",
-    false);
-
-static IntFlag indexMode(
-    { "--index-mode" },
-    "index pulse source (0=drive, 1=300 RPM fake source, 2=360 RPM fake source",
-    0);
+    1);

 static bool high_density = false;

@@ -35,10 +24,6 @@ public:
    HardwareFluxSource(unsigned drive):
        _drive(drive)
    {
-        usbSetDrive(_drive, high_density, indexMode);
-        std::cerr << "Measuring rotational speed... " << std::flush;
-        _oneRevolution = usbGetRotationalPeriod();
-        std::cerr << fmt::format("{}ms\n", _oneRevolution / 1e6);
    }

    ~HardwareFluxSource()
@@ -48,9 +33,9 @@ public:
 public:
    std::unique_ptr<Fluxmap> readFlux(int track, int side)
    {
-        usbSetDrive(_drive, high_density, indexMode);
+        usbSetDrive(_drive, high_density);
        usbSeek(track);
-        Bytes crunched = usbRead(side, synced, revolutions * _oneRevolution);
+        Bytes crunched = usbRead(side, revolutions);
        auto fluxmap = std::make_unique<Fluxmap>();
        fluxmap->appendBytes(crunched.uncrunch());
        return fluxmap;
@@ -69,19 +54,13 @@ public:
 private:
    unsigned _drive;
    unsigned _revolutions;
-    nanoseconds_t _oneRevolution;
 };

-void setHardwareFluxSourceRevolutions(double revolutions)
+void setHardwareFluxSourceRevolutions(int revolutions)
 {
    ::revolutions.setDefaultValue(revolutions);
 }

-void setHardwareFluxSourceSynced(bool synced)
-{
-    ::synced.setDefaultValue(synced);
-}
-
 std::unique_ptr<FluxSource> FluxSource::createHardwareFluxSource(unsigned drive)
 {
    return std::unique_ptr<FluxSource>(new HardwareFluxSource(drive));
--- a/lib/reader.cc
+++ b/lib/reader.cc
@@ -46,11 +46,7 @@ static SettableFlag justRead(

 static SettableFlag dumpRecords(
 	{ "--dump-records" },
-	"Dump the parsed but undecoded records.");
-
-static SettableFlag dumpSectors(
-	{ "--dump-sectors" },
-	"Dump the decoded sectors.");
+	"Dump the parsed records.");

 static IntFlag retries(
 	{ "--retries" },
@@ -223,7 +219,10 @@ void readDiskCommand(AbstractDecoder& decoder)
                std::cout << "giving up" << std::endl
                          << "       ";
            else
+            {
 				std::cout << retry << " retries remaining" << std::endl;
+                track->fluxsource->recalibrate();
+            }
 		}

 		if (dumpRecords)
@@ -231,27 +230,13 @@ void readDiskCommand(AbstractDecoder& decoder)
 			std::cout << "\nRaw (undecoded) records follow:\n\n";
 			for (auto& record : track->rawrecords)
 			{
-				std::cout << fmt::format("I+{:.2f}us with {:.2f}us clock\n",
-                            record.position.ns() / 1000.0, record.clock / 1000.0);
+				std::cout << fmt::format("I+{:.2f}us", record.position.ns() / 1000.0)
+						<< std::endl;
 				hexdump(std::cout, record.data);
 				std::cout << std::endl;
 			}
 		}

-        if (dumpSectors)
-        {
-            std::cout << "\nDecoded sectors follow:\n\n";
-            for (auto& i : readSectors)
-            {
-                auto& sector = i.second;
-				std::cout << fmt::format("{}.{:02}.{:02}: I+{:.2f}us with {:.2f}us clock\n",
-                            sector->logicalTrack, sector->logicalSide, sector->logicalSector,
-                            sector->position.ns() / 1000.0, sector->clock / 1000.0);
-				hexdump(std::cout, sector->data);
-				std::cout << std::endl;
-            }
-        }
-
        int size = 0;
 		bool printedTrack = false;
        for (auto& i : readSectors)
--- a/lib/usb.cc
+++ b/lib/usb.cc
@@ -149,7 +149,7 @@ nanoseconds_t usbGetRotationalPeriod(void)
    usb_cmd_send(&f, f.f.size);

    auto r = await_reply<struct speed_frame>(F_FRAME_MEASURE_SPEED_REPLY);
-    return r->period_ms * 1000000;
+    return r->period_ms * 1000;
 }

 static int large_bulk_transfer(int ep, Bytes& bytes)
@@ -202,16 +202,13 @@ void usbTestBulkTransport()
    await_reply<struct any_frame>(F_FRAME_BULK_TEST_REPLY);
 }

-Bytes usbRead(int side, bool synced, nanoseconds_t readTime)
+Bytes usbRead(int side, int revolutions)
 {
    struct read_frame f = {
        .f = { .type = F_FRAME_READ_CMD, .size = sizeof(f) },
        .side = (uint8_t) side,
-        .synced = (uint8_t) synced
+        .revolutions = (uint8_t) revolutions
    };
-    uint16_t milliseconds = readTime / 1e6;
-    ((uint8_t*)&f.milliseconds)[0] = milliseconds;
-    ((uint8_t*)&f.milliseconds)[1] = milliseconds >> 8;
    usb_cmd_send(&f, f.f.size);

    auto fluxmap = std::unique_ptr<Fluxmap>(new Fluxmap);
@@ -256,51 +253,15 @@ void usbErase(int side)
    await_reply<struct any_frame>(F_FRAME_ERASE_REPLY);
 }

-void usbSetDrive(int drive, bool high_density, int index_mode)
+void usbSetDrive(int drive, bool high_density)
 {
    usb_init();

    struct set_drive_frame f = {
        { .type = F_FRAME_SET_DRIVE_CMD, .size = sizeof(f) },
-        .drive = (uint8_t) drive,
-        .high_density = high_density,
-        .index_mode = (uint8_t) index_mode
+        .drive_flags = (uint8_t)((drive ? DRIVE_1 : DRIVE_0) | (high_density ? DRIVE_HD : DRIVE_DD)),
    };
    usb_cmd_send(&f, f.f.size);
    await_reply<struct any_frame>(F_FRAME_SET_DRIVE_REPLY);
 }

-/* Hacky: the board always operates in little-endian mode. */
-static uint16_t read_short_from_usb(uint16_t usb)
-{
-    uint8_t* p = (uint8_t*)&usb;
-    return p[0] | (p[1] << 8);
-}
-
-static void convert_voltages_from_usb(const struct voltages& vin, struct voltages& vout)
-{
-    vout.logic0_mv = read_short_from_usb(vin.logic0_mv);
-    vout.logic1_mv = read_short_from_usb(vin.logic1_mv);
-}
-
-void usbMeasureVoltages(struct voltages_frame* voltages)
-{
-    usb_init();
-
-    struct any_frame f = {
-        { .type = F_FRAME_MEASURE_VOLTAGES_CMD, .size = sizeof(f) },
-    };
-    usb_cmd_send(&f, f.f.size);
-
-    struct voltages_frame* r = await_reply<struct voltages_frame>(F_FRAME_MEASURE_VOLTAGES_REPLY);
-    convert_voltages_from_usb(r->input_both_off, voltages->input_both_off);
-    convert_voltages_from_usb(r->input_drive_0_selected, voltages->input_drive_0_selected);
-    convert_voltages_from_usb(r->input_drive_1_selected, voltages->input_drive_1_selected);
-    convert_voltages_from_usb(r->input_drive_0_running, voltages->input_drive_0_running);
-    convert_voltages_from_usb(r->input_drive_1_running, voltages->input_drive_1_running);
-    convert_voltages_from_usb(r->output_both_off, voltages->output_both_off);
-    convert_voltages_from_usb(r->output_drive_0_selected, voltages->output_drive_0_selected);
-    convert_voltages_from_usb(r->output_drive_1_selected, voltages->output_drive_1_selected);
-    convert_voltages_from_usb(r->output_drive_0_running, voltages->output_drive_0_running);
-    convert_voltages_from_usb(r->output_drive_1_running, voltages->output_drive_1_running);
-}
--- a/lib/usb.h
+++ b/lib/usb.h
@@ -9,10 +9,9 @@ extern void usbRecalibrate();
 extern void usbSeek(int track);
 extern nanoseconds_t usbGetRotationalPeriod();
 extern void usbTestBulkTransport();
-extern Bytes usbRead(int side, bool synced, nanoseconds_t readTime);
+extern Bytes usbRead(int side, int revolutions);
 extern void usbWrite(int side, const Bytes& bytes);
 extern void usbErase(int side);
-extern void usbSetDrive(int drive, bool high_density, int index_mode);
-extern void usbMeasureVoltages(struct voltages_frame* voltages);
+extern void usbSetDrive(int drive, bool high_density);

 #endif
--- a/lib/writer.cc
+++ b/lib/writer.cc
@@ -15,7 +15,7 @@
 #include "sector.h"
 #include "sectorset.h"

-FlagGroup writerFlags { &hardwareFluxSourceFlags, &hardwareFluxSinkFlags };
+FlagGroup writerFlags { &hardwareFluxSourceFlags };

 static DataSpecFlag dest(
    { "--dest", "-d" },
--- a/mkninja.sh
+++ b/mkninja.sh
@@ -44,27 +44,18 @@ buildlibrary() {
        esac
    done

-    local oobjs
-	local dobjs
-    oobjs=
-	dobjs=
+    local objs
+    objs=
    for src in "$@"; do
        local obj
-        obj="$OBJDIR/opt/${src%%.c*}.o"
-        oobjs="$oobjs $obj"
+        obj="$OBJDIR/${src%%.c*}.o"
+        objs="$objs $obj"

        echo build $obj : cxx $src
-        echo "    flags=$flags $COPTFLAGS"
-
-        obj="$OBJDIR/dbg/${src%%.c*}.o"
-        dobjs="$dobjs $obj"
-
-        echo build $obj : cxx $src
-        echo "    flags=$flags $CDBGFLAGS"
+        echo "    flags=$flags"
    done

-    echo build $OBJDIR/opt/$lib : library $oobjs
-    echo build $OBJDIR/dbg/$lib : library $dobjs
+    echo build $OBJDIR/$lib : library $objs
 }

 buildprogram() {
@@ -86,21 +77,16 @@ buildprogram() {
        esac
    done

-    local oobjs
-	local dobjs
-    oobjs=
-	dobjs=
+    local objs
+    objs=
    for src in "$@"; do
-        oobjs="$oobjs $OBJDIR/opt/$src"
-        dobjs="$dobjs $OBJDIR/dbg/$src"
+        objs="$objs $OBJDIR/$src"
    done

-    echo build $prog-debug$EXTENSION : link $dobjs
-    echo "    flags=$flags $LDDBGFLAGS"
-
-    echo build $prog$EXTENSION : link $oobjs
-    echo "    flags=$flags $LDOPTFLAGS"
+    echo build $prog-debug$EXTENSION : link $objs
+    echo "    flags=$flags"

+    echo build $prog$EXTENSION : strip $prog-debug$EXTENSION
 }

 buildsimpleprogram() {
@@ -159,8 +145,6 @@ buildlibrary libbackend.a \
 	lib/imagewriter/ldbsimagewriter.cc \
    arch/aeslanier/decoder.cc \
    arch/amiga/decoder.cc \
-    arch/amiga/encoder.cc \
-    arch/amiga/amiga.cc \
    arch/apple2/decoder.cc \
    arch/brother/decoder.cc \
    arch/brother/encoder.cc \
@@ -221,6 +205,7 @@ buildlibrary libfrontend.a \
    src/fe-readfb100.cc \
    src/fe-readibm.cc \
    src/fe-readmac.cc \
+    src/fe-readmicrobee.cc \
    src/fe-readmx.cc \
    src/fe-readvictor9k.cc \
    src/fe-readzilogmcz.cc \
@@ -228,9 +213,7 @@ buildlibrary libfrontend.a \
    src/fe-scptoflux.cc \
    src/fe-seek.cc \
    src/fe-testbulktransport.cc \
-    src/fe-testvoltages.cc \
    src/fe-upgradefluxfile.cc \
-    src/fe-writeamiga.cc \
    src/fe-writebrother.cc \
    src/fe-writeflux.cc \
    src/fe-writetestpattern.cc \
@@ -251,13 +234,6 @@ buildsimpleprogram brother120tool \
    libemu.a \
    libfmt.a \

-buildsimpleprogram brother240tool \
-	-Idep/emu \
-    tools/brother240tool.cc \
-    libbackend.a \
-    libemu.a \
-    libfmt.a \
-
 runtest bitaccumulator-test tests/bitaccumulator.cc
 runtest bytes-test          tests/bytes.cc
 runtest compression-test    tests/compression.cc
@@ -268,4 +244,3 @@ runtest fluxpattern-test    tests/fluxpattern.cc
 runtest fmmfm-test          tests/fmmfm.cc
 runtest kryoflux-test       tests/kryoflux.cc
 runtest ldbs-test           tests/ldbs.cc
-runtest amiga-test          tests/amiga.cc
--- a/protocol.h
+++ b/protocol.h
@@ -3,7 +3,7 @@

 enum 
 {
-    FLUXENGINE_VERSION = 11,
+    FLUXENGINE_VERSION = 8,

    FLUXENGINE_VID = 0x1209,
    FLUXENGINE_PID = 0x6e00,
@@ -62,8 +62,6 @@ enum
    F_FRAME_RECALIBRATE_REPLY,    /* any_frame */
    F_FRAME_SET_DRIVE_CMD,        /* setdrive_frame */
    F_FRAME_SET_DRIVE_REPLY,      /* any_frame */
-    F_FRAME_MEASURE_VOLTAGES_CMD, /* any_frame */
-    F_FRAME_MEASURE_VOLTAGES_REPLY, /* voltages_frame */
 };

 enum
@@ -75,13 +73,6 @@ enum
    F_ERROR_INTERNAL,
 };

-enum
-{
-    F_INDEX_REAL,
-    F_INDEX_300,
-    F_INDEX_360
-};
-
 enum
 {
    F_OP_PULSE = 0x80,
@@ -133,8 +124,7 @@ struct read_frame
 {
    struct frame_header f;
    uint8_t side;
-    uint8_t synced;
-    uint16_t milliseconds;
+    uint8_t revolutions;
 };

 struct write_frame
@@ -153,30 +143,7 @@ struct erase_frame
 struct set_drive_frame
 {
    struct frame_header f;
-    uint8_t drive;
-    uint8_t high_density;
-    uint8_t index_mode;
-};
-
-struct voltages
-{
-    uint16_t logic0_mv;
-    uint16_t logic1_mv;
-};
-
-struct voltages_frame
-{
-    struct frame_header f;
-    struct voltages output_both_off;
-    struct voltages output_drive_0_selected;
-    struct voltages output_drive_1_selected;
-    struct voltages output_drive_0_running;
-    struct voltages output_drive_1_running;
-    struct voltages input_both_off;
-    struct voltages input_drive_0_selected;
-    struct voltages input_drive_1_selected;
-    struct voltages input_drive_0_running;
-    struct voltages input_drive_1_running;
+    uint8_t drive_flags;
 };

 #endif
--- a/src/fe-fluxtoscp.cc
+++ b/src/fe-fluxtoscp.cc
@@ -85,7 +85,7 @@ int mainConvertFluxToScp(int argc, const char* argv[])
    fileheader.file_id[0] = 'S';
    fileheader.file_id[1] = 'C';
    fileheader.file_id[2] = 'P';
-    fileheader.version = 0x18; /* Version 1.8 of the spec */
+    fileheader.file_id[3] = 0x18; /* Version 1.8 of the spec */
    fileheader.type = diskType;
    fileheader.revolutions = 5;
    fileheader.start_track = 0;
--- a/src/fe-readaeslanier.cc
+++ b/src/fe-readaeslanier.cc
@@ -12,6 +12,11 @@

 static FlagGroup flags { &readerFlags };

+static StringFlag outputFilename(
+    { "--output", "-o" },
+    "The output image file to write to.",
+    "aeslanier.img");
+
 int mainReadAESLanier(int argc, const char* argv[])
 {
 	setReaderDefaultSource(":t=0-79:s=0");
--- a/src/fe-readmicrobee.cc
+++ b/src/fe-readmicrobee.cc
@@ -0,0 +1,30 @@
+#include "globals.h"
+#include "flags.h"
+#include "reader.h"
+#include "fluxmap.h"
+#include "decoders/decoders.h"
+#include "image.h"
+#include "sector.h"
+#include "sectorset.h"
+#include "record.h"
+#include "ibm/ibm.h"
+#include "fmt/format.h"
+
+static FlagGroup flags { &readerFlags };
+
+static IntFlag sectorIdBase(
+	{ "--sector-id-base" },
+	"Sector ID of the first sector.",
+	0);
+
+int mainReadMicrobee(int argc, const char* argv[])
+{
+	setReaderDefaultSource(":t=0-79:s=0-1");
+	setReaderDefaultOutput("adfs.img");
+    flags.parseFlags(argc, argv);
+
+	IbmDecoder decoder(sectorIdBase);
+	readDiskCommand(decoder);
+    return 0;
+}
+
--- a/src/fe-readmx.cc
+++ b/src/fe-readmx.cc
@@ -8,6 +8,7 @@
 #include "sector.h"
 #include "sectorset.h"
 #include "record.h"
+#include <fmt/format.h>

 static FlagGroup flags { &readerFlags };

--- a/src/fe-rpm.cc
+++ b/src/fe-rpm.cc
@@ -2,7 +2,6 @@
 #include "flags.h"
 #include "usb.h"
 #include "dataspec.h"
-#include "protocol.h"

 static FlagGroup flags;

@@ -16,18 +15,9 @@ int mainRpm(int argc, const char* argv[])
    flags.parseFlags(argc, argv);

    FluxSpec spec(source);
-    usbSetDrive(spec.drive, false, F_INDEX_REAL);
+    usbSetDrive(spec.drive, false);
    nanoseconds_t period = usbGetRotationalPeriod();
-    if (period != 0)
-        std::cout << "Rotational period is " << period/1000000 << " ms (" << 60e9/period << " rpm)" << std::endl;
-    else
-    {
-        std::cout << "No index pulses detected from the disk. Common causes of this are:\n"
-                     "  - no drive is connected\n"
-                     "  - the drive doesn't have an index sensor (e.g. BBC Micro drives)\n"
-                     "  - the disk has no index holes (e.g. reversed flippy disks)\n"
-                     "  - (most common) no disk is inserted in the drive!\n";
-    }
+    std::cout << "Rotational period is " << period/1000 << " ms (" << 60e6/period << " rpm)" << std::endl;

    return 0;
 }
--- a/src/fe-seek.cc
+++ b/src/fe-seek.cc
@@ -1,7 +1,6 @@
 #include "globals.h"
 #include "flags.h"
 #include "usb.h"
-#include "protocol.h"

 static FlagGroup flags;

@@ -19,7 +18,7 @@ int mainSeek(int argc, const char* argv[])
 {
    flags.parseFlags(argc, argv);

-    usbSetDrive(drive, false, F_INDEX_REAL);
+    usbSetDrive(drive, false);
    usbSeek(track);
    return 0;
 }
--- a/src/fe-testvoltages.cc
+++ b/src/fe-testvoltages.cc
@@ -1,47 +0,0 @@
-#include "globals.h"
-#include "flags.h"
-#include "usb.h"
-#include "protocol.h"
-#include <fmt/format.h>
-
-static FlagGroup flags;
-
-static std::string display_voltages(struct voltages& v)
-{
-    return fmt::format(
-        "      Logic 1 / 0:  {:.2f}V / {:.2f}V\n",
-        v.logic0_mv / 1000.0,
-        v.logic1_mv / 1000.0);
-}
-
-int mainTestVoltages(int argc, const char* argv[])
-{
-    flags.parseFlags(argc, argv);
-    struct voltages_frame f;
-    usbMeasureVoltages(&f);
-
-    std::cout << "Output voltages:\n"
-              << "  Both drives deselected\n"
-              << display_voltages(f.output_both_off)
-              << "  Drive 0 selected\n"
-              << display_voltages(f.output_drive_0_selected)
-              << "  Drive 1 selected\n"
-              << display_voltages(f.output_drive_1_selected)
-              << "  Drive 0 running\n"
-              << display_voltages(f.output_drive_0_running)
-              << "  Drive 1 running\n"
-              << display_voltages(f.output_drive_1_running)
-              << "Input voltages:\n"
-              << "  Both drives deselected\n"
-              << display_voltages(f.input_both_off)
-              << "  Drive 0 selected\n"
-              << display_voltages(f.input_drive_0_selected)
-              << "  Drive 1 selected\n"
-              << display_voltages(f.input_drive_1_selected)
-              << "  Drive 0 running\n"
-              << display_voltages(f.input_drive_0_running)
-              << "  Drive 1 running\n"
-              << display_voltages(f.input_drive_1_running);
-
-    return 0;
-}
--- a/src/fe-writeamiga.cc
+++ b/src/fe-writeamiga.cc
@@ -1,23 +0,0 @@
-#include "globals.h"
-#include "flags.h"
-#include "decoders/decoders.h"
-#include "amiga/amiga.h"
-#include "writer.h"
-#include "fmt/format.h"
-#include "image.h"
-#include <fstream>
-
-static FlagGroup flags { &writerFlags, &amigaEncoderFlags };
-
-int mainWriteAmiga(int argc, const char* argv[])
-{
-    setWriterDefaultInput(":c=80:h=2:s=11:b=512");
-    setWriterDefaultDest(":d=0:t=0-79:s=0-1");
-    flags.parseFlags(argc, argv);
-
-	AmigaEncoder encoder;
-	writeDiskCommand(encoder);
-
-    return 0;
-}
-
--- a/src/fluxengine.cc
+++ b/src/fluxengine.cc
@@ -21,15 +21,14 @@ extern command_cb mainReadF85;
 extern command_cb mainReadFB100;
 extern command_cb mainReadIBM;
 extern command_cb mainReadMac;
+extern command_cb mainReadMicrobee;
 extern command_cb mainReadMx;
 extern command_cb mainReadVictor9K;
 extern command_cb mainReadZilogMCZ;
 extern command_cb mainRpm;
 extern command_cb mainSeek;
 extern command_cb mainTestBulkTransport;
-extern command_cb mainTestVoltages;
 extern command_cb mainUpgradeFluxFile;
-extern command_cb mainWriteAmiga;
 extern command_cb mainWriteBrother;
 extern command_cb mainWriteFlux;
 extern command_cb mainWriteTestPattern;
@@ -44,7 +43,6 @@ struct Command
 static command_cb mainRead;
 static command_cb mainWrite;
 static command_cb mainConvert;
-static command_cb mainTest;

 static std::vector<Command> commands =
 {
@@ -54,7 +52,7 @@ static std::vector<Command> commands =
    { "read",              mainRead,              "Reads a disk, producing a sector image.", },
    { "rpm",               mainRpm,               "Measures the disk rotational speed.", },
    { "seek",              mainSeek,              "Moves the disk head.", },
-    { "test",              mainTest,              "Various testing commands.", },
+    { "testbulktransport", mainTestBulkTransport, "Measures your USB bandwidth.", },
    { "upgradefluxfile",   mainUpgradeFluxFile,   "Upgrades a flux file from a previous version of this software.", },
    { "write",             mainWrite,             "Writes a sector image to a disk.", },
    { "writeflux",         mainWriteFlux,         "Writes a raw flux file. Warning: you can't use this to copy disks.", },
@@ -75,6 +73,7 @@ static std::vector<Command> readables =
    { "fb100",         mainReadFB100,     "Reads FB100 disks.", },
    { "ibm",           mainReadIBM,       "Reads the ubiquitous IBM format disks.", },
    { "mac",           mainReadMac,       "Reads Apple Macintosh disks.", },
+    { "microbee",      mainReadMicrobee,  "Reads Microbee disks.", },
    { "mx",            mainReadMx,        "Reads MX disks.", },
    { "victor9k",      mainReadVictor9K,  "Reads Victor 9000 disks.", },
    { "zilogmcz",      mainReadZilogMCZ,  "Reads Zilog MCZ disks.", },
@@ -82,7 +81,6 @@ static std::vector<Command> readables =

 static std::vector<Command> writeables =
 {
-    { "amiga",         mainWriteAmiga,    "Writes Amiga disks.", },
    { "brother",       mainWriteBrother,  "Writes 120kB and 240kB Brother word processor disks.", },
 };

@@ -95,12 +93,6 @@ static std::vector<Command> convertables =
    { "fluxtovcd",     mainConvertFluxToVcd, "Converts (one track of a) flux file to a VCD file.", },
 };

-static std::vector<Command> testables =
-{
-    { "bulktransport", mainTestBulkTransport, "Measures your USB bandwidth.", },
-    { "voltages",      mainTestVoltages,      "Measures the FDD bus voltages.", },
-};
-
 static void extendedHelp(std::vector<Command>& subcommands, const std::string& command)
 {
    std::cout << "fluxengine: syntax: fluxengine " << command << " <format> [<flags>...]\n"
@@ -141,9 +133,6 @@ static int mainWrite(int argc, const char* argv[])
 static int mainConvert(int argc, const char* argv[])
 { return mainExtended(convertables, "convert", argc, argv); }

-static int mainTest(int argc, const char* argv[])
-{ return mainExtended(testables, "test", argc, argv); }
-
 static void help()
 {
    std::cout << "fluxengine: syntax: fluxengine <command> [<flags>...]\n"
--- a/tests/amiga.cc
+++ b/tests/amiga.cc
@@ -1,38 +0,0 @@
-#include "globals.h"
-#include "bytes.h"
-#include "record.h"
-#include "decoders/decoders.h"
-#include "arch/amiga/amiga.h"
-#include <assert.h>
-
-static const Bytes testData = {
-    0x52, /* 0101 0010 */
-    0xff, /* 1111 1111 */
-    0x4a, /* 0100 1010 */
-    0x22, /* 0010 0010 */
-};
-static const Bytes testDataInterleaved = {
-    0x1f, /* 0001 1111 */
-    0x35, /* 0011 0101 */
-    0xcf, /* 1100 1111 */
-    0x80, /* 1000 0000 */
-};
-
-static void testInterleave(void)
-{
-    Bytes interleaved = amigaInterleave(testData);
-    assert(interleaved == testDataInterleaved);
-}
-
-static void testDeinterleave(void)
-{
-    Bytes deinterleaved = amigaDeinterleave(testDataInterleaved);
-    assert(deinterleaved == testData);
-}
-
-int main(int argc, const char* argv[])
-{
-    testDeinterleave();
-    testInterleave();
-    return 0;
-}
--- a/tools/brother240tool.cc
+++ b/tools/brother240tool.cc
@@ -1,56 +0,0 @@
-#include "globals.h"
-#include "fmt/format.h"
-#include <fstream>
-
-static std::fstream inputFile;
-
-void syntax()
-{
-    std::cout << "Syntax: brother240tool <image>\n"
-                 "The disk image will be flipped from Brother to DOS format and back\n"
-                 "again.\n";
-    exit(0);
-}
-
-uint8_t getbyte(uint32_t offset)
-{
-    inputFile.seekg(offset, std::ifstream::beg);
-    return inputFile.get();
-}
-
-void putbyte(uint32_t offset, uint8_t value)
-{
-    inputFile.seekp(offset, std::ifstream::beg);
-    inputFile.put(value);
-}
-
-int main(int argc, const char* argv[])
-{
-    if (argc < 2)
-        syntax();
-    
-    inputFile.open(argv[1], std::ios::in | std::ios::out | std::ios::binary);
-    if (!inputFile.is_open())
-		Error() << fmt::format("cannot open input file '{}'", argv[1]);
-
-    uint8_t b1 = getbyte(0x015);
-    uint8_t b2 = getbyte(0x100);
-    if ((b1 == 0x58) && (b2 == 0x58))
-    {
-        std::cerr << "Flipping from Brother to DOS.\n";
-        putbyte(0x015, 0xf0);
-        putbyte(0x100, 0xf0);
-    }
-    else if ((b1 == 0xf0) && (b2 == 0xf0))
-    {
-        std::cerr << "Flipping from DOS to Brother.\n";
-        putbyte(0x015, 0x58);
-        putbyte(0x100, 0x58);
-    }
-    else
-        Error() << "Unknown image format.";
-
-    inputFile.close();
-    return 0;
-}
-
Author	SHA1	Message	Date
David Given	a97e961842	Merge from master.	2019-10-14 22:27:26 +02:00
David Given	3c8c64c0b4	Skeleton, non-functional microbee front end.	2019-08-26 23:15:45 +02:00