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Avoid bug when using Repl.

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This commit is contained in:
Bastian Löher
2023-01-13 01:28:02 +01:00
parent 89559d21aa
commit 10595b068d
4 changed files with 21 additions and 5 deletions
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1
09_branches/soc.py
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@@ -182,7 +182,6 @@ class SOC(Elaboratable):
export(isLoad, "isLoad")
export(isStore, "isStore")
export(isSystem, "isSystem")
export(rdId, "rdId")
export(rs1Id, "rs1Id")
export(rs2Id, "rs2Id")
export(Iimm, "Iimm")

3
10_lui_auipc/soc.py
View File

@@ -62,7 +62,7 @@ class SOC(Elaboratable):
isSystem = (instr[0:7] == 0b1110011)
# Immediate format decoder
Uimm = (Cat(Repl(0, 12), instr[12:32]))
Uimm = (Cat(Const(0, 12), instr[12:32]))
Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
@@ -183,7 +183,6 @@ class SOC(Elaboratable):
export(isLoad, "isLoad")
export(isStore, "isStore")
export(isSystem, "isSystem")
export(rdId, "rdId")
export(rs1Id, "rs1Id")
export(rs2Id, "rs2Id")
export(Iimm, "Iimm")

2
11_modules/cpu.py
View File

@@ -48,7 +48,7 @@ class CPU(Elaboratable):
self.isSystem = isSystem
# Immediate format decoder
Uimm = Cat(Repl(0, 12), instr[12:32])
Uimm = Cat(Const(0, 12), instr[12:32])
Iimm = Cat(instr[20:31], Repl(instr[31], 21))
Simm = Cat(instr[7:12], instr[25:31], Repl(instr[31], 21))
Bimm = Cat(0, instr[8:12], instr[25:31], instr[7],

20
boards/top.py
View File

@@ -13,8 +13,26 @@ class Top(Elaboratable):
if step == 1:
path = "01_blink"
if step == 2:
elif step == 2:
path = "02_slower_blinky"
elif step == 3:
path = "03_blink_from_rom"
elif step == 4:
path = "04_instruction_decoder"
elif step == 5:
path = "05_register_bank"
elif step == 6:
path = "06_alu"
elif step == 7:
path = "07_assembler"
elif step == 8:
path = "08_jumps"
elif step == 9:
path = "09_branches"
elif step == 10:
path = "10_lui_auipc"
elif step == 11:
path = "11_modules"
else:
print("Invalid step_number {}.".format(step))
exit(1)