Change clockworks module, because clock domain names are not propagated up the hierarchy anymore (RFC59).

02_slower_blinky/soc.py

@@ -19,7 +19,7 @@ class SOC(wiring.Component):
         count = Signal(5)
 
         # Instantiate the clockwork with a divider of 2^21
-        cw = Clockworks(slow=21)
+        cw = Clockworks(m, slow=21)
 
         # Add the clockwork to the top module. If this is not done,
         # the logic will not be instantiated.

03_blink_from_rom/soc.py

@@ -12,7 +12,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21)
+        cw = Clockworks(m, slow=21)
         m.submodules.cw = cw
 
         sequence = [

04_instruction_decoder/soc.py

@@ -16,7 +16,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21)
+        cw = Clockworks(m, slow=21)
         m.submodules.cw = cw
 
         # Instruction sequence to be executed

05_register_bank/soc.py

@@ -16,7 +16,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Instruction sequence to be executed

06_alu/soc.py

@@ -16,7 +16,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Instruction sequence to be executed

07_assembler/soc.py

@@ -38,7 +38,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Program counter

08_jumps/soc.py

@@ -30,7 +30,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Program counter

09_branches/soc.py

@@ -31,7 +31,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Program counter

10_lui_auipc/soc.py

@@ -28,7 +28,7 @@ class SOC(Elaboratable):
 
         m = Module()
 
-        cw = Clockworks(slow=21, sim_slow=10)
+        cw = Clockworks(m, slow=21, sim_slow=10)
         m.submodules.cw = cw
 
         # Program counter

11_modules/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks(slow=19, sim_slow=10)
+        cw = Clockworks(m, slow=19, sim_slow=10)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

12_size_optimisation/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks(slow=19, sim_slow=10)
+        cw = Clockworks(m, slow=19, sim_slow=10)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

13_subroutines/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

14_subroutines_v2/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

15_load/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

16_store/soc.py

@@ -17,7 +17,7 @@ class SOC(Elaboratable):
     def elaborate(self, platform):
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Memory())
         cpu = DomainRenamer("slow")(CPU())
         m.submodules.cw = cw

17_memory_map/soc.py

@@ -22,7 +22,7 @@ class SOC(Elaboratable):
         print("clock frequency = {}".format(clk_frequency))
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Mem())
         cpu = DomainRenamer("slow")(CPU())
         uart_tx = DomainRenamer("slow")(

18_mandelbrot/soc.py

@@ -22,7 +22,7 @@ class SOC(Elaboratable):
         print("clock frequency = {}".format(clk_frequency))
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Mem())
         cpu = DomainRenamer("slow")(CPU())
         uart_tx = DomainRenamer("slow")(

lib/clockworks.py

@@ -4,11 +4,16 @@ from amaranth.lib.wiring import In, Out
 
 # This module handles clock division and provides a new 'slow' clock domain
 
+clockworks_domain_name = "slow"
+
 class Clockworks(wiring.Component):
 
     o_slow: Out(1)
 
-    def __init__(self, slow=0, sim_slow=None):
+    def __init__(self, module, slow=0, sim_slow=None):
+
+        # Since amaranth 0.6 clock domains do not propagate upwards (RFC59)
+        module.domains += ClockDomain(clockworks_domain_name)
 
         # Since the module provides a new clock domain, which is accessible
         # via the top level module, we don't need to explicitly provide the

tests/soc.py

@@ -21,7 +21,7 @@ class SOC(Elaboratable):
         simulation = platform is None
 
         m = Module()
-        cw = Clockworks()
+        cw = Clockworks(m)
         memory = DomainRenamer("slow")(Mem(simulation=simulation))
         cpu = DomainRenamer("slow")(CPU())
         uart_tx = DomainRenamer("slow")(