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learn-fpga-amaranth
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a3c011ee3190ef0022e6edceb375335cd0780562
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Bastian Löher
a3c011ee31
Start step7 with riscv assembler.
2022-12-05 10:58:54 +01:00
01_blink
Factor out SOC and add bench test.
2022-12-01 16:07:26 +01:00
02_slower_blinky
Move clockworks to lib. Add env.sh for PYTHONPATH. Fix step03.
2022-12-05 00:38:11 +01:00
03_blink_from_rom
Move clockworks to lib. Add env.sh for PYTHONPATH. Fix step03.
2022-12-05 00:38:11 +01:00
04_instruction_decoder
Reorder.
2022-12-05 03:34:02 +01:00
05_register_bank
Whitespace.
2022-12-05 04:05:29 +01:00
06_alu
fsm must run in 'slow' domain. alu must be combinatorial.
2022-12-05 10:44:03 +01:00
07_assembler
Start step7 with riscv assembler.
2022-12-05 10:58:54 +01:00
lib
Add slow_sim parameter to clockworks. Add step6 / alu.
2022-12-05 08:38:34 +01:00
tools
Start step7 with riscv assembler.
2022-12-05 10:58:54 +01:00
.gitignore
Add step5.
2022-12-05 04:05:18 +01:00
env.sh
Start step7 with riscv assembler.
2022-12-05 10:58:54 +01:00
Description
mirrored from
https://github.com/bl0x/learn-fpga-amaranth
138
KiB
Languages
Python
99.3%
Shell
0.2%
Assembly
0.2%
Makefile
0.1%
