62 lines
2.2 KiB
Python
62 lines
2.2 KiB
Python
from amaranth import *
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from amaranth.sim import *
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from soc import SOC
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soc = SOC()
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sim = Simulator(soc)
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prev_clk = 0
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def proc():
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cpu = soc.cpu
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mem = soc.memory
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while True:
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global prev_clk
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clk = yield soc.slow_clk
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if prev_clk == 0 and prev_clk != clk:
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state = (yield soc.cpu.fsm.state)
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if state == 2:
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print("-- NEW CYCLE -----------------------")
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print(" F: LEDS = {:05b}".format((yield soc.leds)))
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print(" F: pc={}".format((yield cpu.pc)))
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print(" F: instr={:#032b}".format((yield cpu.instr)))
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if (yield cpu.isALUreg):
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print(" ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield cpu.rdId), (yield cpu.rs1Id), (yield cpu.rs2Id),
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(yield cpu.funct3)))
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if (yield cpu.isALUimm):
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print(" ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield cpu.rdId), (yield cpu.rs1Id), (yield cpu.Iimm),
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(yield cpu.funct3)))
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if (yield cpu.isBranch):
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print(" BRANCH rs1={} rs2={}".format(
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(yield cpu.rs1Id), (yield cpu.rs2Id)))
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if (yield cpu.isLoad):
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print(" LOAD")
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if (yield cpu.isStore):
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print(" STORE")
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if (yield cpu.isSystem):
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print(" SYSTEM")
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break
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if state == 4:
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print(" R: LEDS = {:05b}".format((yield soc.leds)))
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print(" R: rs1={}".format((yield cpu.rs1)))
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print(" R: rs2={}".format((yield cpu.rs2)))
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if state == 1:
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print(" E: LEDS = {:05b}".format((yield soc.leds)))
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print(" E: Writeback x{} = {:032b}".format((yield cpu.rdId),
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(yield cpu.writeBackData)))
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if state == 8:
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print(" NEW")
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yield
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prev_clk = clk
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('bench.vcd', 'bench.gtkw', traces=soc.ports):
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# Let's run for a quite long time
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sim.run_until(2, )
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