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Mux added, and some cleanup

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This commit is contained in:
Scott Alfter
2024-06-13 13:03:38 -07:00
parent 990bad228c
commit 841881d543
15 changed files with 166 additions and 92 deletions
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9
Makefile
View File

@@ -1,6 +1,15 @@
clean:
-rm *.vcd *.vvp
mux_tb: mux_tb.vcd
gtkwave mux_tb.vcd &
mux_tb.vcd: mux_tb.vvp
vvp mux_tb.vvp
mux_tb.vvp: mux.v mux_tb.v
iverilog -o mux_tb.vvp mux_tb.v
xor_tb: xor_tb.vcd
gtkwave xor_tb.vcd &

8
and.v
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@@ -4,13 +4,13 @@
`include "nand.v"
`include "not.v"
module And (in1, in2, out);
input wire in1;
input wire in2;
module And (a, b, out);
input wire a;
input wire b;
output wire out;
wire out_bar;
Nand u1(.in1(in1), .in2(in2), .out(out_bar));
Nand u1(.a(a), .b(b), .out(out_bar));
Not u2(.in(out_bar), .out(out));
endmodule

26
and_tb.v
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@@ -1,21 +1,23 @@
`include "and.v"
module And_test;
reg in1=0;
reg in2=0;
reg a=0;
reg b=0;
wire out;
integer i;
initial begin
$dumpfile("and_tb.vcd");
$dumpvars;
#1 in1=1;
#1 begin
in1=0;
in2=1;
end;
#1 in1=1;
#1 $finish();
$dumpfile("and_tb.vcd");
$dumpvars;
for (i=0; i<4; i=i+1)
begin
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
And u1(.in1(in1), .in2(in2), .out(out));
And u1(.a(a), .b(b), .out(out));
endmodule

24
mux.v Normal file
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@@ -0,0 +1,24 @@
`ifndef _mux_v
`define _mux_v
`include "not.v"
`include "and.v"
`include "or.v"
module Mux (a, b, sel, out);
input wire a;
input wire b;
input wire sel;
output wire out;
wire sel_bar;
wire a_sel;
wire b_sel;
Not u1 (.in(sel), .out(sel_bar));
And u2 (.a(a), .b(sel_bar), .out(a_sel));
And u3 (.a(b), .b(sel), .out(b_sel));
Or u4 (.a(a_sel), .b(b_sel), .out(out));
endmodule
`endif

25
mux_tb.v Normal file
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@@ -0,0 +1,25 @@
`include "mux.v"
module Mux_test;
reg a=0;
reg b=0;
reg sel=0;
wire out;
integer i;
initial begin
$dumpfile("mux_tb.vcd");
$dumpvars;
for (i=0; i<8; i=i+1)
begin
sel=(i&4)>>2;
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
Mux u1(.a(a), .b(b), .sel(sel), .out(out));
endmodule

8
nand.v
View File

@@ -1,12 +1,12 @@
`ifndef _nand_v
`define _nand_v
module Nand (in1, in2, out);
input wire in1;
input wire in2;
module Nand (a, b, out);
input wire a;
input wire b;
output wire out;
assign out=~(in1&&in2);
assign out=~(a&&b);
endmodule
`endif

26
nand_tb.v
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@@ -1,21 +1,23 @@
`include "nand.v"
module Nand_test;
reg in1=0;
reg in2=0;
reg a=0;
reg b=0;
wire out;
integer i;
initial begin
$dumpfile("nand_tb.vcd");
$dumpvars;
#1 in1=1;
#1 begin
in1=0;
in2=1;
end;
#1 in1=1;
#1 $finish();
$dumpfile("nand_tb.vcd");
$dumpvars;
for (i=0; i<4; i=i+1)
begin
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
Nand u1(.in1(in1), .in2(in2), .out(out));
Nand u1(.a(a), .b(b), .out(out));
endmodule

8
nor.v
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@@ -4,13 +4,13 @@
`include "or.v"
`include "not.v"
module Nor (in1, in2, out);
input wire in1;
input wire in2;
module Nor (a, b, out);
input wire a;
input wire b;
output wire out;
wire out_bar;
Or u1(.in1(in1), .in2(in2), .out(out_bar));
Or u1(.a(a), .b(b), .out(out_bar));
Not u2(.in(out_bar), .out(out));
endmodule

26
nor_tb.v
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@@ -1,21 +1,23 @@
`include "nor.v"
module Nor_test;
reg in1=0;
reg in2=0;
reg a=0;
reg b=0;
wire out;
integer i;
initial begin
$dumpfile("nor_tb.vcd");
$dumpvars;
#1 in1=1;
#1 begin
in1=0;
in2=1;
end;
#1 in1=1;
#1 $finish();
$dumpfile("nor_tb.vcd");
$dumpvars;
for (i=0; i<4; i=i+1)
begin
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
Nor u1(.in1(in1), .in2(in2), .out(out));
Nor u1(.a(a), .b(b), .out(out));
endmodule

2
not.v
View File

@@ -7,7 +7,7 @@ module Not (in, out);
input wire in;
output wire out;
Nand u1(.in1(in), .in2(in), .out(out));
Nand u1(.a(in), .b(in), .out(out));
endmodule
`endif

14
not_tb.v
View File

@@ -4,11 +4,17 @@ module Not_test;
reg in=0;
wire out;
integer i;
initial begin
$dumpfile("not_tb.vcd");
$dumpvars;
#1 in=1;
#1 $finish();
$dumpfile("not_tb.vcd");
$dumpvars;
for (i=0; i<2; i=i+1)
begin
in=i;
#1;
end
$finish();
end
Not u1(.in(in), .out(out));

16
or.v
View File

@@ -4,16 +4,16 @@
`include "nand.v"
`include "not.v"
module Or (in1, in2, out);
input wire in1;
input wire in2;
module Or (a, b, out);
input wire a;
input wire b;
output wire out;
wire in1_bar;
wire in2_bar;
wire a_bar;
wire b_bar;
Not u1(.in(in1), .out(in1_bar));
Not u2(.in(in2), .out(in2_bar));
Nand u3(.in1(in1_bar), .in2(in2_bar), .out(out));
Not u1(.in(a), .out(a_bar));
Not u2(.in(b), .out(b_bar));
Nand u3(.a(a_bar), .b(b_bar), .out(out));
endmodule
`endif

26
or_tb.v
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@@ -1,21 +1,23 @@
`include "or.v"
module Or_test;
reg in1=0;
reg in2=0;
reg a=0;
reg b=0;
wire out;
integer i;
initial begin
$dumpfile("or_tb.vcd");
$dumpvars;
#1 in1=1;
#1 begin
in1=0;
in2=1;
end;
#1 in1=1;
#1 $finish();
$dumpfile("or_tb.vcd");
$dumpvars;
for (i=0; i<4; i=i+1)
begin
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
Or u1(.in1(in1), .in2(in2), .out(out));
Or u1(.a(a), .b(b), .out(out));
endmodule

14
xor.v
View File

@@ -3,19 +3,19 @@
`include "nand.v"
module Xor (in1, in2, out);
input wire in1;
input wire in2;
module Xor (a, b, out);
input wire a;
input wire b;
output wire out;
wire tmp1;
wire tmp2;
wire tmp3;
Nand u1(.in1(in1), .in2(in2), .out(tmp1));
Nand u2(.in1(in1), .in2(tmp1), .out(tmp2));
Nand u3(.in1(in2), .in2(tmp1), .out(tmp3));
Nand u4(.in1(tmp2), .in2(tmp3), .out(out));
Nand u1(.a(a), .b(b), .out(tmp1));
Nand u2(.a(a), .b(tmp1), .out(tmp2));
Nand u3(.a(b), .b(tmp1), .out(tmp3));
Nand u4(.a(tmp2), .b(tmp3), .out(out));
endmodule
`endif

26
xor_tb.v
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@@ -1,21 +1,23 @@
`include "xor.v"
module Xor_test;
reg in1=0;
reg in2=0;
reg a=0;
reg b=0;
wire out;
integer i;
initial begin
$dumpfile("xor_tb.vcd");
$dumpvars;
#1 in1=1;
#1 begin
in1=0;
in2=1;
end;
#1 in1=1;
#1 $finish();
$dumpfile("xor_tb.vcd");
$dumpvars;
for (i=0; i<4; i=i+1)
begin
b=(i&2)>>1;
a=i&1;
#1;
end
$finish();
end
Xor u1(.in1(in1), .in2(in2), .out(out));
Xor u1(.a(a), .b(b), .out(out));
endmodule