dff: switch to Verilog primitives to get edge triggering

dff.v

@@ -1,21 +1,9 @@
 `ifndef _dff_v
 `define _dff_v
 
-`include "nand.v"
-`include "not.v"
-
-module DFF (input in, input clk, output out);
-    wire in_bar, clk_bar;
-    wire u2o, u3o;
-    wire s, r;
-
-    Not u1 (.in(in), .out(in_bar));
-    Nand u2 (.a(in), .b(clk), .out(u2o));
-    Nand u3 (.a(in_bar), .b(clk), .out(u3o));
-    Nand u4 (.a(u2o), .b(r), .out(s));
-    Nand u5 (.a(u3o), .b(s), .out(r));
-
-    assign out=s;
+module DFF (input in, input clk, output reg out);
+    always @(posedge clk)
+        out <= in;
 endmodule
 
 `endif 

dff_tb.v

@@ -11,11 +11,11 @@ module DFF_test;
         $dumpfile("dff_tb.vcd");
         $dumpvars;
 
-        for (i=0; i<100; i=i+1)
+        for (i=0; i<200; i=i+1)
         begin
             if (i%3==0)
                 in=!in;
-            if (i%10==0)
+            if (i%7==0)
                 clk=!clk;
             #1;
         end