initial commit: implement a NAND gate, and test it

.gitignore

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+*~
+*.vcd
+*.vvp
+nohup.out

Makefile

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+clean:
+	-rm *.vcd *.vvp
+
+nand_tb: nand_tb.vcd
+	gtkwave nand_tb.vcd &
+
+nand_tb.vcd: nand_tb.vvp
+	vvp nand_tb.vvp
+
+nand_tb.vvp: nand.v nand_tb.v
+	iverilog -o nand_tb.vvp nand_tb.v

README.md

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+nand2tetris_verilog
+===================
+
+My attempt at learning Verilog by using it to implement the 
+[From Nand to Tetris](https://www.nand2tetris.org/) design.  Initial stages 
+need Icarus Verilog, GTKWave, and make to test.
+

nand.v

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+module Nand (in1, in2, out);
+    input wire in1;
+    input wire in2;
+    output wire out;
+
+    assign out=~(in1&&in2);
+endmodule

nand_tb.v

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+`include "nand.v"
+module Nand_test;
+    reg in1=0;
+    reg in2=0;
+    wire out;
+
+    initial begin
+       $dumpfile("nand_tb.vcd");
+       $dumpvars;
+       #1 in1=1;
+       #1 begin
+        in1=0; 
+        in2=1;
+       end;
+       #1 in1=1;
+       #1 $finish();
+    end
+
+    Nand u1(.in1(in1), .in2(in2), .out(out));
+endmodule