16-bit increment

This commit is contained in:
2024-06-13 21:19:30 -07:00
parent a7f7723702
commit ec1a0731cd
3 changed files with 50 additions and 0 deletions

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@@ -1,6 +1,15 @@
clean:
-rm *.vcd *.vvp
inc16_tb: inc16_tb.vcd
gtkwave inc16_tb.vcd &
inc16_tb.vcd: inc16_tb.vvp
vvp inc16_tb.vvp
inc16_tb.vvp: inc16.v inc16_tb.v
iverilog -o inc16_tb.vvp inc16_tb.v
add16_tb: add16_tb.vcd
gtkwave add16_tb.vcd &

21
inc16.v Normal file
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`ifndef _inc16_v
`define _inc16_v
`include "halfadder.v"
module Inc16 (input [15:0] in, output [15:0] out);
wire [16:1] c;
genvar i;
generate
for (i=0; i<16; i=i+1)
begin
if (i==0)
HalfAdder u1 (.a(in[i]), .b(1'b1), .sum(out[i]), .carry(c[i+1]));
else
HalfAdder u1 (.a(in[i]), .b(c[i]), .sum(out[i]), .carry(c[i+1]));
end
endgenerate
endmodule
`endif

20
inc16_tb.v Normal file
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`include "inc16.v"
module Inc16_test;
reg [15:0] in;
wire [15:0] out;
integer i;
initial begin
$dumpfile("inc16_tb.vcd");
$dumpvars;
in=123;
#1;
in=16'h7F;
#1;
$finish();
end
Inc16 u1(.in(in), .out(out));
endmodule