Demux

Makefile

@@ -10,6 +10,15 @@ not16_tb.vcd: not16_tb.vvp
 not16_tb.vvp: not16.v not16_tb.v
 	iverilog -o not16_tb.vvp not16_tb.v
 
+dmux_tb: dmux_tb.vcd
+	gtkwave dmux_tb.vcd &
+
+dmux_tb.vcd: dmux_tb.vvp
+	vvp dmux_tb.vvp
+
+dmux_tb.vvp: dmux.v dmux_tb.v
+	iverilog -o dmux_tb.vvp dmux_tb.v
+
 mux_tb: mux_tb.vcd
 	gtkwave mux_tb.vcd &
 

dmux.v

@@ -0,0 +1,17 @@
+`ifndef _mux_v
+`define _mux_v
+
+`include "not.v"
+`include "and.v"
+
+module DMux (input in, input sel, output a, output b);
+    wire sel_bar;
+    wire a_sel;
+    wire b_sel;
+
+    Not u1 (.in(sel), .out(sel_bar));
+    And u2 (.a(in), .b(sel_bar), .out(a));
+    And u3 (.a(in), .b(sel), .out(b));
+endmodule
+
+`endif

dmux_tb.v

@@ -0,0 +1,23 @@
+`include "dmux.v"
+
+module DMux_test;
+    reg in=0;
+    reg sel=0;
+    wire a, b;
+
+    integer i;
+
+    initial begin
+        $dumpfile("dmux_tb.vcd");
+        $dumpvars;
+        for (i=0; i<4; i=i+1)
+        begin
+            sel=(i&2)>>1;
+            in=i&1;
+            #1;
+        end
+        $finish();
+    end
+
+    DMux u1(.in(in), .sel(sel), .a(a), .b(b));
+endmodule