16 lines
267 B
Verilog
16 lines
267 B
Verilog
`ifndef _and16_v
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`define _and16_v
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`include "and.v"
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module And16 (input [15:0] a, input [15:0] b, output [15:0] out);
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genvar i;
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generate
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for (i=0; i<16; i=i+1)
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And u1 (.a(a[i]), .b(b[i]), .out(out[i]));
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endgenerate
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endmodule
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`endif
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