and16 and or16

Makefile

@@ -1,6 +1,24 @@
 clean:
 	-rm *.vcd *.vvp
 
+or16_tb: or16_tb.vcd
+	gtkwave or16_tb.vcd &
+
+or16_tb.vcd: or16_tb.vvp
+	vvp or16_tb.vvp
+
+or16_tb.vvp: or16.v or16_tb.v
+	iverilog -o or16_tb.vvp or16_tb.v
+
+and16_tb: and16_tb.vcd
+	gtkwave and16_tb.vcd &
+
+and16_tb.vcd: and16_tb.vvp
+	vvp and16_tb.vvp
+
+and16_tb.vvp: and16.v and16_tb.v
+	iverilog -o and16_tb.vvp and16_tb.v
+
 not16_tb: not16_tb.vcd
 	gtkwave not16_tb.vcd &
 

and16.v

@@ -0,0 +1,15 @@
+`ifndef _and16_v
+`define _and16_v
+
+`include "and.v"
+
+module And16 (input [15:0] a, input [15:0] b, output [15:0] out);
+
+    genvar i;
+    generate
+        for (i=0; i<16; i=i+1)
+            And u1 (.a(a[i]), .b(b[i]), .out(out[i]));
+    endgenerate
+endmodule
+
+`endif

and16_tb.v

@@ -0,0 +1,32 @@
+`include "and16.v"
+
+module And16_test;
+    reg [15:0] a, b;
+    wire [15:0] out;
+
+    integer i, j;
+
+    initial begin
+        $dumpfile("and16_tb.vcd");
+        $dumpvars;
+        for (i=0; i<16; i=i+1)
+        begin
+            a[i]=0;
+            b[i]=0;
+        end
+        for (i=15; i>=0; i=i-1)
+        begin
+            for (j=0; j<4; j=j+1)
+            begin
+                b[i]=(j&2)>>1;
+                a[i]=j&1;
+                #1;
+            end
+            a[i]=0;
+            b[i]=0;
+        end
+        $finish();
+    end
+
+    And16 u1 (.a(a), .b(b), .out(out));
+endmodule

or16.v

@@ -0,0 +1,15 @@
+`ifndef _or16_v
+`define _or16_v
+
+`include "or.v"
+
+module Or16 (input [15:0] a, input [15:0] b, output [15:0] out);
+
+    genvar i;
+    generate
+        for (i=0; i<16; i=i+1)
+            Or u1 (.a(a[i]), .b(b[i]), .out(out[i]));
+    endgenerate
+endmodule
+
+`endif

or16_tb.v

@@ -0,0 +1,32 @@
+`include "or16.v"
+
+module Or16_test;
+    reg [15:0] a, b;
+    wire [15:0] out;
+
+    integer i, j;
+
+    initial begin
+        $dumpfile("or16_tb.vcd");
+        $dumpvars;
+        for (i=0; i<16; i=i+1)
+        begin
+            a[i]=0;
+            b[i]=0;
+        end
+        for (i=15; i>=0; i=i-1)
+        begin
+            for (j=0; j<4; j=j+1)
+            begin
+                b[i]=(j&2)>>1;
+                a[i]=j&1;
+                #1;
+            end
+            a[i]=0;
+            b[i]=0;
+        end
+        $finish();
+    end
+
+    Or16 u1 (.a(a), .b(b), .out(out));
+endmodule