33 lines
591 B
Verilog
33 lines
591 B
Verilog
`include "and16.v"
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module And16_test;
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reg [15:0] a, b;
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wire [15:0] out;
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integer i, j;
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initial begin
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$dumpfile("and16_tb.vcd");
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$dumpvars;
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for (i=0; i<16; i=i+1)
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begin
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a[i]=0;
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b[i]=0;
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end
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for (i=15; i>=0; i=i-1)
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begin
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for (j=0; j<4; j=j+1)
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begin
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b[i]=(j&2)>>1;
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a[i]=j&1;
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#1;
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end
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a[i]=0;
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b[i]=0;
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end
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$finish();
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end
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And16 u1 (.a(a), .b(b), .out(out));
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endmodule
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