13 lines
248 B
Verilog
13 lines
248 B
Verilog
`ifndef _bit_v
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`define _bit_v
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`include "dff.v"
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`include "mux.v"
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module Bit (input in, input load, input clk, output out);
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wire i;
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Mux u1 (.a(out), .b(in), .sel(load), .out(i));
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DFF u2 (.in(i), .clk(clk), .out(out));
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endmodule
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`endif
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