bit: timing's a bit wonky

Makefile

@@ -1,6 +1,15 @@
 clean:
 	-rm *.vcd *.vvp
 
+bit_tb: bit_tb.vcd
+	gtkwave bit_tb.vcd &
+
+bit_tb.vcd: bit_tb.vvp
+	vvp bit_tb.vvp
+
+bit_tb.vvp: bit.v bit_tb.v
+	iverilog -o bit_tb.vvp bit_tb.v
+
 dff_tb: dff_tb.vcd
 	gtkwave dff_tb.vcd &
 

bit.v

@@ -0,0 +1,13 @@
+`ifndef _bit_v
+`define _bit_v
+
+`include "dff.v"
+`include "mux.v"
+
+module Bit (input in, input load, input clk, output out);
+    wire i;
+    Mux u1 (.a(out), .b(in), .sel(load), .out(i));
+    DFF u2 (.in(i), .clk(clk), .out(out));
+endmodule
+
+`endif 

bit_tb.v

@@ -0,0 +1,31 @@
+`include "bit.v"
+
+module Bit_test;
+    reg in=0;
+    reg load=0;
+    reg clk=0;
+    wire out;
+
+    integer i;
+
+    initial begin
+        $dumpfile("bit_tb.vcd");
+        $dumpvars;
+
+        for (i=0; i<200; i=i+1)
+        begin
+            clk=!clk;
+            if (i%17==0)
+                in=!in;
+            if (i%13==0)
+                load=1;
+            if (i%13==3)
+                load=0;
+            #1;
+        end
+
+        $finish();
+    end
+
+    Bit u1 (.in(in), .load(load), .clk(clk), .out(out));
+endmodule