31 lines
520 B
Verilog
31 lines
520 B
Verilog
`include "bit.v"
|
|
|
|
module Bit_test;
|
|
reg in=0;
|
|
reg load=0;
|
|
reg clk=0;
|
|
wire out;
|
|
|
|
integer i;
|
|
|
|
initial begin
|
|
$dumpfile("bit_tb.vcd");
|
|
$dumpvars;
|
|
|
|
for (i=0; i<200; i=i+1)
|
|
begin
|
|
clk=!clk;
|
|
if (i%17==0)
|
|
in=!in;
|
|
if (i%13==0)
|
|
load=1;
|
|
if (i%13==3)
|
|
load=0;
|
|
#1;
|
|
end
|
|
|
|
$finish();
|
|
end
|
|
|
|
Bit u1 (.in(in), .load(load), .clk(clk), .out(out));
|
|
endmodule |