27 lines
420 B
Verilog
27 lines
420 B
Verilog
`include "dff.v"
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module DFF_test;
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reg in=0;
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reg clk=0;
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wire out;
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integer i;
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initial begin
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$dumpfile("dff_tb.vcd");
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$dumpvars;
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for (i=0; i<200; i=i+1)
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begin
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if (i%3==0)
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in=!in;
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if (i%7==0)
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clk=!clk;
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#1;
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end
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$finish();
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end
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DFF u1 (.in(in), .clk(clk), .out(out));
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endmodule |