18 lines
312 B
Verilog
18 lines
312 B
Verilog
`ifndef _dmux_v
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`define _dmux_v
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`include "not.v"
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`include "and.v"
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module DMux (input in, input sel, output a, output b);
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wire sel_bar;
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wire a_sel;
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wire b_sel;
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Not u1 (.in(sel), .out(sel_bar));
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And u2 (.a(in), .b(sel_bar), .out(a));
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And u3 (.a(in), .b(sel), .out(b));
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endmodule
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`endif
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