1-to-4 demux

Makefile

@@ -1,6 +1,15 @@
 clean:
 	-rm *.vcd *.vvp
 
+dmux4way_tb: dmux4way_tb.vcd
+	gtkwave dmux4way_tb.vcd &
+
+dmux4way_tb.vcd: dmux4way_tb.vvp
+	vvp dmux4way_tb.vvp
+
+dmux4way_tb.vvp: dmux4way.v dmux4way_tb.v
+	iverilog -o dmux4way_tb.vvp dmux4way_tb.v
+
 mux8way16_tb: mux8way16_tb.vcd
 	gtkwave mux8way16_tb.vcd &
 

dmux.v

@@ -1,5 +1,5 @@
-`ifndef _mux_v
-`define _mux_v
+`ifndef _dmux_v
+`define _dmux_v
 
 `include "not.v"
 `include "and.v"

dmux4way.v

@@ -0,0 +1,14 @@
+`ifndef _dmux4way_v
+`define _dmux4way_v
+
+`include "dmux.v"
+
+module DMux4Way (input in, input [1:0] sel, output a, output b, output c, output d);
+    wire temp0, temp1;
+
+    DMux u1 (.in(in), .sel(sel[1]), .a(temp0), .b(temp1));
+    DMux u2 (.in(temp0), .sel(sel[0]), .a(a), .b(b));
+    DMux u3 (.in(temp1), .sel(sel[0]), .a(c), .b(d));
+endmodule
+
+`endif

dmux4way_tb.v

@@ -0,0 +1,22 @@
+`include "dmux4way.v"
+
+module DMux4Way_test;
+    reg in=1;
+    reg [1:0] sel=0;
+    wire a, b, c, d;
+
+    integer i;
+
+    initial begin
+        $dumpfile("dmux4way_tb.vcd");
+        $dumpvars;
+        for (i=0; i<4; i=i+1)
+        begin
+            sel=i;
+            #1;
+        end
+        $finish();
+    end
+
+    DMux4Way u1(.in(in), .sel(sel), .a(a), .b(b), .c(c), .d(d));
+endmodule