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nand2tetris_verilog/dmux4way.v
2024-06-13 18:55:53 -07:00

15 lines
354 B
Verilog

`ifndef _dmux4way_v
`define _dmux4way_v
`include "dmux.v"
module DMux4Way (input in, input [1:0] sel, output a, output b, output c, output d);
wire temp0, temp1;
DMux u1 (.in(in), .sel(sel[1]), .a(temp0), .b(temp1));
DMux u2 (.in(temp0), .sel(sel[0]), .a(a), .b(b));
DMux u3 (.in(temp1), .sel(sel[0]), .a(c), .b(d));
endmodule
`endif