23 lines
387 B
Verilog
23 lines
387 B
Verilog
`include "dmux4way.v"
|
|
|
|
module DMux4Way_test;
|
|
reg in=1;
|
|
reg [1:0] sel=0;
|
|
wire a, b, c, d;
|
|
|
|
integer i;
|
|
|
|
initial begin
|
|
$dumpfile("dmux4way_tb.vcd");
|
|
$dumpvars;
|
|
for (i=0; i<4; i=i+1)
|
|
begin
|
|
sel=i;
|
|
#1;
|
|
end
|
|
$finish();
|
|
end
|
|
|
|
DMux4Way u1(.in(in), .sel(sel), .a(a), .b(b), .c(c), .d(d));
|
|
endmodule
|