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nand2tetris_verilog/dmux8way.v
2024-06-13 19:00:21 -07:00

16 lines
456 B
Verilog

`ifndef _dmux8way_v
`define _dmux8way_v
`include "dmux.v"
`include "dmux4way.v"
module DMux8Way (input in, input [2:0] sel, output a, output b, output c, output d, output e, output f, output g, output h);
wire temp0, temp1;
DMux u1 (.in(in), .sel(sel[2]), .a(temp0), .b(temp1));
DMux4Way u2 (.in(temp0), .sel(sel[1:0]), .a(a), .b(b), .c(c), .d(d));
DMux4Way u3 (.in(temp1), .sel(sel[1:0]), .a(e), .b(f), .c(g), .d(h));
endmodule
`endif