1-to-8 demux

This commit is contained in:
2024-06-13 19:00:21 -07:00
parent 66539bedd9
commit 23220d1004
3 changed files with 46 additions and 0 deletions

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@@ -1,6 +1,15 @@
clean:
-rm *.vcd *.vvp
dmux8way_tb: dmux8way_tb.vcd
gtkwave dmux8way_tb.vcd &
dmux8way_tb.vcd: dmux8way_tb.vvp
vvp dmux8way_tb.vvp
dmux8way_tb.vvp: dmux8way.v dmux8way_tb.v
iverilog -o dmux8way_tb.vvp dmux8way_tb.v
dmux4way_tb: dmux4way_tb.vcd
gtkwave dmux4way_tb.vcd &

15
dmux8way.v Normal file
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`ifndef _dmux8way_v
`define _dmux8way_v
`include "dmux.v"
`include "dmux4way.v"
module DMux8Way (input in, input [2:0] sel, output a, output b, output c, output d, output e, output f, output g, output h);
wire temp0, temp1;
DMux u1 (.in(in), .sel(sel[2]), .a(temp0), .b(temp1));
DMux4Way u2 (.in(temp0), .sel(sel[1:0]), .a(a), .b(b), .c(c), .d(d));
DMux4Way u3 (.in(temp1), .sel(sel[1:0]), .a(e), .b(f), .c(g), .d(h));
endmodule
`endif

22
dmux8way_tb.v Normal file
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`include "dmux8way.v"
module DMux8Way_test;
reg in=1;
reg [2:0] sel=0;
wire a, b, c, d;
integer i;
initial begin
$dumpfile("dmux8way_tb.vcd");
$dumpvars;
for (i=0; i<8; i=i+1)
begin
sel=i;
#1;
end
$finish();
end
DMux8Way u1(.in(in), .sel(sel), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h));
endmodule