1-to-8 demux
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9
Makefile
9
Makefile
@@ -1,6 +1,15 @@
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clean:
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-rm *.vcd *.vvp
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dmux8way_tb: dmux8way_tb.vcd
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gtkwave dmux8way_tb.vcd &
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dmux8way_tb.vcd: dmux8way_tb.vvp
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vvp dmux8way_tb.vvp
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dmux8way_tb.vvp: dmux8way.v dmux8way_tb.v
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iverilog -o dmux8way_tb.vvp dmux8way_tb.v
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dmux4way_tb: dmux4way_tb.vcd
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gtkwave dmux4way_tb.vcd &
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15
dmux8way.v
Normal file
15
dmux8way.v
Normal file
@@ -0,0 +1,15 @@
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`ifndef _dmux8way_v
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`define _dmux8way_v
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`include "dmux.v"
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`include "dmux4way.v"
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module DMux8Way (input in, input [2:0] sel, output a, output b, output c, output d, output e, output f, output g, output h);
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wire temp0, temp1;
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DMux u1 (.in(in), .sel(sel[2]), .a(temp0), .b(temp1));
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DMux4Way u2 (.in(temp0), .sel(sel[1:0]), .a(a), .b(b), .c(c), .d(d));
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DMux4Way u3 (.in(temp1), .sel(sel[1:0]), .a(e), .b(f), .c(g), .d(h));
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endmodule
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`endif
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22
dmux8way_tb.v
Normal file
22
dmux8way_tb.v
Normal file
@@ -0,0 +1,22 @@
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`include "dmux8way.v"
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module DMux8Way_test;
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reg in=1;
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reg [2:0] sel=0;
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wire a, b, c, d;
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integer i;
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initial begin
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$dumpfile("dmux8way_tb.vcd");
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$dumpvars;
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for (i=0; i<8; i=i+1)
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begin
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sel=i;
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#1;
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end
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$finish();
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end
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DMux8Way u1(.in(in), .sel(sel), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h));
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endmodule
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