23 lines
415 B
Verilog
23 lines
415 B
Verilog
`include "dmux8way.v"
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module DMux8Way_test;
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reg in=1;
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reg [2:0] sel=0;
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wire a, b, c, d;
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integer i;
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initial begin
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$dumpfile("dmux8way_tb.vcd");
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$dumpvars;
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for (i=0; i<8; i=i+1)
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begin
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sel=i;
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#1;
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end
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$finish();
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end
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DMux8Way u1(.in(in), .sel(sel), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h));
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endmodule
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