24 lines
372 B
Verilog
24 lines
372 B
Verilog
`include "dmux.v"
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module DMux_test;
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reg in=0;
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reg sel=0;
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wire a, b;
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integer i;
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initial begin
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$dumpfile("dmux_tb.vcd");
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$dumpvars;
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for (i=0; i<4; i=i+1)
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begin
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sel=(i&2)>>1;
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in=i&1;
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#1;
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end
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$finish();
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end
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DMux u1(.in(in), .sel(sel), .a(a), .b(b));
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endmodule
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