16 lines
411 B
Verilog
16 lines
411 B
Verilog
`ifndef _fulladder_v
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`define _fulladder_v
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`include "halfadder.v"
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`include "or.v"
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module FullAdder (input a, input b, input c, output sum, output carry);
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wire halfsum, halfcarry1, halfcarry2;
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HalfAdder u1 (.a(a), .b(b), .sum(halfsum), .carry(halfcarry1));
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HalfAdder u2 (.a(halfsum), .b(c), .sum(sum), .carry(halfcarry2));
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Or u3 (.a(halfcarry1), .b(halfcarry2), .out(carry));
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endmodule
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`endif
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