24 lines
423 B
Verilog
24 lines
423 B
Verilog
`include "fulladder.v"
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module FullAdder_test;
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reg a, b, c;
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wire [1:0] sum;
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integer i;
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initial begin
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$dumpfile("fulladder_tb.vcd");
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$dumpvars;
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for (i=0; i<8; i=i+1)
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begin
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c=(i&4)>>2;
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b=(i&2)>>1;
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a=i&1;
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#1;
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end
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$finish();
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end
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FullAdder u1(.a(a), .b(b), .c(c), .sum(sum[0]), .carry(sum[1]));
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endmodule
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