13 lines
237 B
Verilog
13 lines
237 B
Verilog
`ifndef _halfadder_v
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`define _halfadder_v
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`include "and.v"
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`include "xor.v"
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module HalfAdder (input a, input b, output sum, output carry);
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Xor u1 (.a(a), .b(b), .out(sum));
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And u2 (.a(a), .b(b), .out(carry));
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endmodule
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`endif
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