21 lines
299 B
Verilog
21 lines
299 B
Verilog
`include "inc16.v"
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module Inc16_test;
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reg [15:0] in;
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wire [15:0] out;
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integer i;
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initial begin
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$dumpfile("inc16_tb.vcd");
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$dumpvars;
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in=123;
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#1;
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in=16'h7F;
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#1;
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$finish();
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end
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Inc16 u1(.in(in), .out(out));
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endmodule
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