15 lines
340 B
Verilog
15 lines
340 B
Verilog
`ifndef _mux4way_v
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`define _mux4way_v
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`include "mux.v"
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module Mux4Way (input a, input b, input c, input d, input [1:0] sel, output out);
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wire tmp0, tmp1;
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Mux u1(.a(a), .b(b), .sel(sel[0]), .out(tmp0));
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Mux u2(.a(c), .b(d), .sel(sel[0]), .out(tmp1));
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Mux u3(.a(tmp0), .b(tmp1), .sel(sel[1]), .out(out));
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endmodule
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`endif
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