15 lines
366 B
Verilog
15 lines
366 B
Verilog
`ifndef _mux4way16_v
|
|
`define _mux4way16_v
|
|
|
|
`include "mux4way.v"
|
|
|
|
module Mux4Way16 (input [15:0] a, input [15:0] b, input [15:0] c, input [15:0] d, input [1:0] sel, output [15:0] out);
|
|
genvar i;
|
|
generate
|
|
for (i=0; i<16; i=i+1)
|
|
Mux4Way u1 (.a(a[i]), .b(b[i]), .c(c[i]), .d(d[i]), .sel(sel), .out(out[i]));
|
|
endgenerate
|
|
endmodule
|
|
|
|
`endif
|