16-bit 4-to-1 mux

Makefile

@@ -10,6 +10,15 @@ mux8way_tb.vcd: mux8way_tb.vvp
 mux8way_tb.vvp: mux8way.v mux8way_tb.v
 	iverilog -o mux8way_tb.vvp mux8way_tb.v
 
+mux4way16_tb: mux4way16_tb.vcd
+	gtkwave mux4way16_tb.vcd &
+
+mux4way16_tb.vcd: mux4way16_tb.vvp
+	vvp mux4way16_tb.vvp
+
+mux4way16_tb.vvp: mux4way16.v mux4way16_tb.v
+	iverilog -o mux4way16_tb.vvp mux4way16_tb.v
+
 mux4way_tb: mux4way_tb.vcd
 	gtkwave mux4way_tb.vcd &
 

mux4way16.v

@@ -0,0 +1,14 @@
+`ifndef _mux4way16_v
+`define _mux4way16_v
+
+`include "mux4way.v"
+
+module Mux4Way16 (input [15:0] a, input [15:0] b, input [15:0] c, input [15:0] d, input [1:0] sel, output [15:0] out);
+    genvar i;
+    generate
+        for (i=0; i<16; i=i+1)
+            Mux4Way u1 (.a(a[i]), .b(b[i]), .c(c[i]), .d(d[i]), .sel(sel), .out(out[i]));
+    endgenerate
+endmodule
+
+`endif

mux4way16_tb.v

@@ -0,0 +1,29 @@
+`include "mux4way16.v"
+
+module Mux4Way16_test;
+    reg [15:0] a, b, c, d;
+    reg [1:0] sel;
+    wire [15:0] out;
+
+    integer i, j;
+
+    initial begin
+        $dumpfile("mux4way16_tb.vcd");
+        $dumpvars;
+        a=16'hDEAD;
+        b=16'hBEEF;
+        c=16'h0000;
+        d=16'hFFFF;
+        sel=0;
+        #1;
+        sel=1;
+        #1;
+        sel=2;
+        #1;
+        sel=3;
+        #1;
+        $finish();
+    end
+
+    Mux4Way16 u1 (.a(a), .b(b), .c(c), .d(d), .sel(sel), .out(out));
+endmodule