30 lines
505 B
Verilog
30 lines
505 B
Verilog
`include "mux4way16.v"
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module Mux4Way16_test;
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reg [15:0] a, b, c, d;
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reg [1:0] sel;
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wire [15:0] out;
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integer i, j;
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initial begin
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$dumpfile("mux4way16_tb.vcd");
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$dumpvars;
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a=16'hDEAD;
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b=16'hBEEF;
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c=16'h0000;
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d=16'hFFFF;
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sel=0;
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#1;
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sel=1;
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#1;
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sel=2;
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#1;
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sel=3;
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#1;
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$finish();
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end
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Mux4Way16 u1 (.a(a), .b(b), .c(c), .d(d), .sel(sel), .out(out));
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endmodule
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