27 lines
482 B
Verilog
27 lines
482 B
Verilog
`include "mux4way.v"
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module Mux4Way_test;
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reg a, b, c, d;
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reg [1:0] sel;
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wire out;
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integer i;
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initial begin
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$dumpfile("mux4way_tb.vcd");
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$dumpvars;
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for (i=0; i<64; i=i+1)
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begin
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sel=(i&48)>>4;
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d=(i&8)>>3;
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c=(i&4)>>2;
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b=(i&2)>>1;
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a=i&1;
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#1;
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end
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$finish();
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end
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Mux4Way u1(.a(a), .b(b), .c(c), .d(d), .sel(sel), .out(out));
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endmodule
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