16 lines
437 B
Verilog
16 lines
437 B
Verilog
`ifndef _mux8way_v
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`define _mux8way_v
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`include "mux4way.v"
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`include "mux.v"
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module Mux8Way (input a, input b, input c, input d, input e, input f, input g, input h, input [2:0] sel, output out);
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wire tmp0, tmp1;
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Mux4Way u1(.a(a), .b(b), .c(c), .d(d), .sel(sel[1:0]), .out(tmp0));
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Mux4Way u2(.a(e), .b(f), .c(g), .d(h), .sel(sel[1:0]), .out(tmp1));
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Mux u3(.a(tmp0), .b(tmp1), .sel(sel[2]), .out(out));
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endmodule
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`endif
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