8-to-1 mux
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9
Makefile
9
Makefile
@@ -1,6 +1,15 @@
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clean:
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-rm *.vcd *.vvp
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mux8way_tb: mux8way_tb.vcd
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gtkwave mux8way_tb.vcd &
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mux8way_tb.vcd: mux8way_tb.vvp
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vvp mux8way_tb.vvp
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mux8way_tb.vvp: mux8way.v mux8way_tb.v
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iverilog -o mux8way_tb.vvp mux8way_tb.v
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mux4way_tb: mux4way_tb.vcd
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gtkwave mux4way_tb.vcd &
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15
mux8way.v
Normal file
15
mux8way.v
Normal file
@@ -0,0 +1,15 @@
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`ifndef _mux8way_v
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`define _mux8way_v
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`include "mux4way.v"
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`include "mux.v"
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module Mux8Way (input a, input b, input c, input d, input e, input f, input g, input h, input [2:0] sel, output out);
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wire tmp0, tmp1;
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Mux4Way u1(.a(a), .b(b), .c(c), .d(d), .sel(sel[1:0]), .out(tmp0));
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Mux4Way u2(.a(e), .b(f), .c(g), .d(h), .sel(sel[1:0]), .out(tmp1));
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Mux u3(.a(tmp0), .b(tmp1), .sel(sel[2]), .out(out));
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endmodule
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`endif
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30
mux8way_tb.v
Normal file
30
mux8way_tb.v
Normal file
@@ -0,0 +1,30 @@
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`include "mux8way.v"
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module Mux8Way_test;
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reg a, b, c, d, e, f, g, h;
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reg [2:0] sel;
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wire out;
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integer i;
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initial begin
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$dumpfile("mux8way_tb.vcd");
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$dumpvars;
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for (i=0; i<2048; i=i+1)
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begin
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sel=(i&1792)>>8;
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h=(i&128)>>7;
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g=(i&64)>>6;
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f=(i&32)>>5;
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e=(i&16)>>4;
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d=(i&8)>>3;
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c=(i&4)>>2;
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b=(i&2)>>1;
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a=i&1;
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#1;
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end
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$finish();
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end
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Mux8Way u1(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .sel(sel), .out(out));
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endmodule
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