19 lines
558 B
Verilog
19 lines
558 B
Verilog
`ifndef _mux8way16_v
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`define _mux8way16_v
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`include "mux8way.v"
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module Mux8Way16 (input [15:0] a, input [15:0] b, input [15:0] c, input [15:0] d,
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input [15:0] e, input [15:0] f, input [15:0] g, input [15:0] h,
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input [2:0] sel, output [15:0] out);
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genvar i;
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generate
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for (i=0; i<16; i=i+1)
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Mux8Way u1 (.a(a[i]), .b(b[i]), .c(c[i]), .d(d[i]),
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.e(e[i]), .f(f[i]), .g(g[i]), .h(h[i]),
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.sel(sel), .out(out[i]));
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endgenerate
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endmodule
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`endif
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