16-bit 8-to-1 mux
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9
Makefile
9
Makefile
@@ -1,6 +1,15 @@
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clean:
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-rm *.vcd *.vvp
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mux8way16_tb: mux8way16_tb.vcd
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gtkwave mux8way16_tb.vcd &
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mux8way16_tb.vcd: mux8way16_tb.vvp
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vvp mux8way16_tb.vvp
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mux8way16_tb.vvp: mux8way16.v mux8way16_tb.v
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iverilog -o mux8way16_tb.vvp mux8way16_tb.v
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mux8way_tb: mux8way_tb.vcd
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gtkwave mux8way_tb.vcd &
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18
mux8way16.v
Normal file
18
mux8way16.v
Normal file
@@ -0,0 +1,18 @@
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`ifndef _mux8way16_v
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`define _mux8way16_v
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`include "mux8way.v"
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module Mux8Way16 (input [15:0] a, input [15:0] b, input [15:0] c, input [15:0] d,
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input [15:0] e, input [15:0] f, input [15:0] g, input [15:0] h,
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input [2:0] sel, output [15:0] out);
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genvar i;
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generate
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for (i=0; i<16; i=i+1)
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Mux8Way u1 (.a(a[i]), .b(b[i]), .c(c[i]), .d(d[i]),
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.e(e[i]), .f(f[i]), .g(g[i]), .h(h[i]),
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.sel(sel), .out(out[i]));
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endgenerate
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endmodule
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`endif
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30
mux8way16_tb.v
Normal file
30
mux8way16_tb.v
Normal file
@@ -0,0 +1,30 @@
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`include "mux8way16.v"
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module Mux8Way16_test;
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reg [15:0] a, b, c, d, e, f, g, h;
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reg [2:0] sel;
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wire [15:0] out;
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integer i;
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initial begin
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$dumpfile("mux8way16_tb.vcd");
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$dumpvars;
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a=16'hDEAD;
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b=16'hBEEF;
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c=16'h0000;
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d=16'hFFFF;
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e=16'h5555;
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f=16'hAAAA;
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g=16'hFEED;
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h=16'hB00F;
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for (i=0; i<8; i=i+1)
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begin
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sel=i;
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#1;
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end
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$finish();
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end
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Mux8Way16 u1 (.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .sel(sel), .out(out));
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endmodule
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