16-bit 8-to-1 mux

This commit is contained in:
2024-06-13 18:28:20 -07:00
parent 2bbde06bec
commit 353fe40507
3 changed files with 57 additions and 0 deletions

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clean:
-rm *.vcd *.vvp
mux8way16_tb: mux8way16_tb.vcd
gtkwave mux8way16_tb.vcd &
mux8way16_tb.vcd: mux8way16_tb.vvp
vvp mux8way16_tb.vvp
mux8way16_tb.vvp: mux8way16.v mux8way16_tb.v
iverilog -o mux8way16_tb.vvp mux8way16_tb.v
mux8way_tb: mux8way_tb.vcd
gtkwave mux8way_tb.vcd &

18
mux8way16.v Normal file
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`ifndef _mux8way16_v
`define _mux8way16_v
`include "mux8way.v"
module Mux8Way16 (input [15:0] a, input [15:0] b, input [15:0] c, input [15:0] d,
input [15:0] e, input [15:0] f, input [15:0] g, input [15:0] h,
input [2:0] sel, output [15:0] out);
genvar i;
generate
for (i=0; i<16; i=i+1)
Mux8Way u1 (.a(a[i]), .b(b[i]), .c(c[i]), .d(d[i]),
.e(e[i]), .f(f[i]), .g(g[i]), .h(h[i]),
.sel(sel), .out(out[i]));
endgenerate
endmodule
`endif

30
mux8way16_tb.v Normal file
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`include "mux8way16.v"
module Mux8Way16_test;
reg [15:0] a, b, c, d, e, f, g, h;
reg [2:0] sel;
wire [15:0] out;
integer i;
initial begin
$dumpfile("mux8way16_tb.vcd");
$dumpvars;
a=16'hDEAD;
b=16'hBEEF;
c=16'h0000;
d=16'hFFFF;
e=16'h5555;
f=16'hAAAA;
g=16'hFEED;
h=16'hB00F;
for (i=0; i<8; i=i+1)
begin
sel=i;
#1;
end
$finish();
end
Mux8Way16 u1 (.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .sel(sel), .out(out));
endmodule