31 lines
605 B
Verilog
31 lines
605 B
Verilog
`include "mux8way16.v"
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module Mux8Way16_test;
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reg [15:0] a, b, c, d, e, f, g, h;
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reg [2:0] sel;
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wire [15:0] out;
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integer i;
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initial begin
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$dumpfile("mux8way16_tb.vcd");
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$dumpvars;
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a=16'hDEAD;
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b=16'hBEEF;
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c=16'h0000;
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d=16'hFFFF;
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e=16'h5555;
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f=16'hAAAA;
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g=16'hFEED;
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h=16'hB00F;
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for (i=0; i<8; i=i+1)
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begin
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sel=i;
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#1;
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end
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$finish();
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end
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Mux8Way16 u1 (.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .sel(sel), .out(out));
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endmodule
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