31 lines
627 B
Verilog
31 lines
627 B
Verilog
`include "mux8way.v"
|
|
|
|
module Mux8Way_test;
|
|
reg a, b, c, d, e, f, g, h;
|
|
reg [2:0] sel;
|
|
wire out;
|
|
|
|
integer i;
|
|
|
|
initial begin
|
|
$dumpfile("mux8way_tb.vcd");
|
|
$dumpvars;
|
|
for (i=0; i<2048; i=i+1)
|
|
begin
|
|
sel=(i&1792)>>8;
|
|
h=(i&128)>>7;
|
|
g=(i&64)>>6;
|
|
f=(i&32)>>5;
|
|
e=(i&16)>>4;
|
|
d=(i&8)>>3;
|
|
c=(i&4)>>2;
|
|
b=(i&2)>>1;
|
|
a=i&1;
|
|
#1;
|
|
end
|
|
$finish();
|
|
end
|
|
|
|
Mux8Way u1(.a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .h(h), .sel(sel), .out(out));
|
|
endmodule
|