24 lines
352 B
Verilog
24 lines
352 B
Verilog
`include "nor.v"
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module Nor_test;
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reg a=0;
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reg b=0;
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wire out;
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integer i;
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initial begin
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$dumpfile("nor_tb.vcd");
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$dumpvars;
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for (i=0; i<4; i=i+1)
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begin
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b=(i&2)>>1;
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a=i&1;
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#1;
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end
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$finish();
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end
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Nor u1(.a(a), .b(b), .out(out));
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endmodule
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